Anuj Pathania
Orcid: 0000-0002-5813-7021Affiliations:
- University of Amsterdam, The Netherlands
- Karlsruhe Institute of Technology, Germany (PhD 2018)
According to our database1,
Anuj Pathania
authored at least 46 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
ACM Trans. Design Autom. Electr. Syst., 2024
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
Analyzing Per-Application Energy Consumption in a Multi-Application Computing Continuum.
Proceedings of the 2024 9th International Conference on Fog and Mobile Edge Computing (FMEC), 2024
2023
ACM Trans. Embed. Comput. Syst., October, 2023
Estimating the Energy Consumption of Applications in the Computing Continuum with iFogSim.
Proceedings of the High Performance Computing, 2023
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
Proceedings of the 29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2023
Proceedings of the 29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems.
ACM Trans. Archit. Code Optim., 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2021
IEEE Trans. Computers, 2021
IEEE Trans. Computers, 2021
T-TSP: Transient-Temperature Based Safe Power Budgeting in Multi-/Many-Core Processors.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Computers, 2020
Unified Thread- and Data-Mapping for Multi-Threaded Multi-Phase Applications on SPM Many-Cores.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
BrezeFlow: Unified Debugger for Android CPU Power Governors and Schedulers on Edge Devices.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
ACM Trans. Embed. Comput. Syst., 2019
IEEE Embed. Syst. Lett., 2019
CoRR, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018
Pareto-Optimal Power- and Cache-Aware Task Mapping for Many-Cores with Distributed Shared Last-Level Cache.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IEEE Trans. Parallel Distributed Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Computers, 2017
ACM Trans. Archit. Code Optim., 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
it Inf. Technol., 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014