Anugerah Firdauzi

According to our database, Anugerah Firdauzi authored at least 5 papers between 2016 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector.

Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

IEICE Trans. Electron., 2019

2018

A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS.

Jian Sen Teh, Liter Siek, Abdel Martinez Alonso, Anugerah Firdauzi, Akira Matsuzawa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator.

Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Electron., 2017

2016

A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC.

Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 2 GHz 3.1 mW type-I digital ring-based PLL.

Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016