Antti Mäntyniemi

Orcid: 0000-0002-1775-5245

According to our database1, Antti Mäntyniemi authored at least 12 papers between 1999 and 2014.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2014
Time-to-digital converter (TDC) based on startable ring oscillators and successive approximation.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

2013
A time-to-digital converter (TDC) with a 13-bit cyclic time domain successive approximation interpolator with sub-ps-level resolution using current DAC and differential switch.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
A Multichannel High-Precision CMOS Time-to-Digital Converter for Laser-Scanner-Based Perception Systems.
IEEE Trans. Instrum. Meas., 2012

A multi-channel wide range time-to-digital converter with better than 9ps RMS precision for pulsed time-of-flight laser rangefinding.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2009
Synchronization in a Multilevel CMOS Time-to-Digital Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method.
IEEE J. Solid State Circuits, 2009

2006
A CMOS time-to-digital converter with better than 10 ps single-shot precision.
IEEE J. Solid State Circuits, 2006

2005
A delay line based CMOS time digitizer IC with 13 ps single-shot precision.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
A CMOS time-to-digital converter based on a ring oscillator for a laser radar.
Proceedings of the ESSCIRC 2003, 2003

2002
A nonlinearity-corrected CMOS time digitizer IC with 20 ps single-shot precision.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
A high resolution digital CMOS time-to-digital converter based on nested delay locked loops.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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