Antonyus Pyetro do Amaral Ferreira

According to our database, Antonyus Pyetro do Amaral Ferreira authored at least 14 papers between 2010 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

An FPGA-based real-time occlusion robust stereo vision system using semi-global matching.

Lucas F. S. Cambuim, Luiz A. Oliveira, Edna Natividade da Silva Barros, Antonyus P. A. Ferreira

J. Real Time Image Process., 2020

An embedded automatic license plate recognition system using deep learning.

Diogo M. F. Izidio, Antonyus P. A. Ferreira, Heitor R. Medeiros, Edna Natividade da Silva Barros

Des. Autom. Embed. Syst., 2020

2019

Latin hypercube initialization strategy for design space exploration of deep neural network architectures.

Heitor R. Medeiros, Diogo M. F. Izidio, Antonyus P. do A. Ferreira, Edna Natividade da Silva Barros

Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2019

Towards better generalization in WLAN positioning systems with genetic algorithms and neural networks.

Diogo M. F. Izidio, Antonyus P. do A. Ferreira, Edna Natividade da Silva Barros

Proceedings of the Genetic and Evolutionary Computation Conference, 2019

2018

An Embedded Automatic License Plate Recognition System Using Deep Learning.

Diogo M. F. Izidio, Antonyus P. A. Ferreira, Edna Natividade da Silva Barros

Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

An FPGA-Based RFID Baseband Processor Using a RISC-V Platform.

Pedro J. A. Ishimaru, Antonyus P. A. Ferreira, Vanessa O. Ogg, Cecil Accetti R. de A. Melo, Edna Natividade da Silva Barros

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

2016

Aceleração da consulta a um grande banco de DNA forense: uma abordagem multiplataforma.

Antonyus Pyetro do Amaral Ferreira

PhD thesis, 2016

A hardware accelerator for the alignment of multiple DNA sequences.

Antonyus Pyetro do Amaral Ferreira, Joao G. M. Silva, Jefferson R. L. Anjos, Luiz H. A. Figueiroa, Edna Natividade da Silva Barros, Manoel Eusébio de Lima, Victor Wanderley Costa de Medeiros

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

An FPGA-based accelerator for multiple real-time template matching.

Erika S. Albuquerque, Antonyus Pyetro do Amaral Ferreira, Joao G. M. Silva, João Paulo Fernandes Barbosa, Renato L. M. Carlos, Djeefther S. Albuquerque, Edna Natividade da Silva Barros

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A hardware accelerator for the alignment of multiple DNA sequences in forensic identification.

Antonyus P. A. Ferreira, Joao G. M. Silva, Jefferson R. L. Anjos, Luiz H. A. Figueiroa, Edna Natividade da Silva Barros, Manoel Eusébio de Lima, Victor Wanderley Costa de Medeiros

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

A high performance hardware accelerator for dynamic texture segmentation.

João Paulo Fernandes Barbosa, Antonyus Pyetro do Amaral Ferreira, Rodrigo Camarotti Ferreira da Rocha, Erika S. Albuquerque, Josivan R. Reis, Djeefther S. Albuquerque, Edna Natividade da Silva Barros

J. Syst. Archit., 2015

2012

FPGA-based architecture to speed-up scientific computation in seismic applications.

Victor Wanderley Costa de Medeiros, Rodrigo Camarotti Ferreira da Rocha, Antonyus Pyetro do Amaral Ferreira, João Paulo Fernandes Barbosa, Abel Guilhermino Silva-Filho, Manoel Eusébio de Lima, Thomas Grosser, Wolfgang Rosenstiel

Int. J. High Perform. Syst. Archit., 2012

2011

Poster: high performance FPGA-based implementation of the seismic modeling of the RTM algorithm.

Victor Wanderley Costa de Medeiros, Rodrigo Camarotti Ferreira da Rocha, Antonyus Pyetro do Amaral Ferreira, Bruno Holanda Tavares Charamba Dutra, Abner Corrêa Barros, João Cleber Bezerra Liborio Correia, João Paulo Fernandes Barbosa, Severino José de Barros-Junior, Gilliano Ginno Silva de Menezes, Abel Guilhermino Silva-Filho, Manoel Eusébio de Lima

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, 2011

2010

A high performance full pipelined arquitecture of MLP Neural Networks in FPGA.

Antonyus Pyetro do Amaral Ferreira, Edna Natividade da Silva Barros

Proceedings of the 17th IEEE International Conference on Electronics, 2010