Antônio Otávio Fernandes

According to our database1, Antônio Otávio Fernandes authored at least 37 papers between 1988 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Arithmetic Circuit Classification Using Convolutional Neural Networks.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

2016
Complexity-Aware Assignment of Latent Values in Discriminative Models for Accurate Gesture Recognition.
Proceedings of the 29th SIBGRAPI Conference on Graphics, Patterns and Images, 2016

2014
A Quantum-Dot Cellular Automata Processor Design.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

2012
Selection of formal verification heuristics for parallel execution.
Int. J. Softw. Tools Technol. Transf., 2012

HydroNode: A low cost, energy efficient, multi purpose node for underwater sensor networks.
Proceedings of the 37th Annual IEEE Conference on Local Computer Networks, 2012

2011
A cache based algorithm to predict HDL modules faults.
Proceedings of the 12th Latin American Test Workshop, 2011

Tracking hardware evolution.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Machine vision applications and development aspects.
Proceedings of the 9th IEEE International Conference on Control and Automation, 2011

2010
A modular CNF-based SAT solver.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

2009
BugTracer: A system for integrated circuit development tracking and statistics retrieval.
Proceedings of the 10th Latin American Test Workshop, 2009

2008
BenCGen: a digital circuit generation tool for benchmarks.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Sensor stream reduction for clustered wireless sensor networks.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

An in-network reduction algorithm for real-time wireless sensor network applications.
Proceedings of the WMuNeP'07, 2008

Improving SAT-based Combinational Equivalence Checking through circuit preprocessing.
Proceedings of the 26th International Conference on Computer Design, 2008

Efficient Allocation of Verification Resources using Revision History Information.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
On The Use Data Reduction Algorithms for Real-Time Wireless Sensor Networks.
Proceedings of the 12th IEEE Symposium on Computers and Communications (ISCC 2007), 2007

A Sampling Data Stream Algorithm For Wireless Sensor Networks.
Proceedings of IEEE International Conference on Communications, 2007

SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause Reuse.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Data Stream Based Algorithms For Wireless Sensor Network Applications.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2006
System-level Dynamic Power Management Techniques for Communication Intensive Devices.
Proceedings of the IFIP VLSI-SoC 2006, 2006

2004
Exception handling in microprocessors using assertion libraries.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2003
The Chip is Ready. Am I done? On-chip Verification using Assertion Processors.
Proceedings of the IFIP VLSI-SoC 2003, 2003

On-Chip Property Verification Using Assertion Processors.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Dynamic Reconfiguration Behavior Using Generic FPGAs and FPIDs.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Scheduling Nodes in Wireless Sensor Networks: A Voronoi Approach.
Proceedings of the 28th Annual IEEE Conference on Local Computer Networks (LCN 2003), 2003

Refactoring digital hardware designs with assertion libraries.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Efficient power management in real-time embedded systems.
Proceedings of 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003

A biomedical wearable device for remote monitoring of physiological signals.
Proceedings of 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003

2001
An Embedded Converter from RS232 to Universal Serial Bus.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

A FPGA Implementation of a DCT-Based Digital Electrocardiographic Signal Compression Device.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

2000
JADE: An Embedded Systems Specification, Code Generation and Optimization Tool.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Wearable Computer as a Multi-parametric Monitor for Physiological Signals.
Proceedings of the 1st IEEE International Symposium on Bioinformatics and Biomedical Engineering, 2000

1999
System-level partitioning with uncertainty.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Implementation of an Edge Detection Algorithm in a Reconfigurable Computing System.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

Hardware-Software Codesign of Embedded Systems.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

1991
A self-checking PLA automatic generator tool based on unordered codes encoding.
Proceedings of the conference on European design automation, 1991

1988
Le test des PLAs optimisés topologiquement. (Test of folded PLAs).
PhD thesis, 1988


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