Antonio J. Acosta
Orcid: 0000-0002-7934-9162Affiliations:
- University of Sevilla, Spain
According to our database1,
Antonio J. Acosta
authored at least 63 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
1995
2000
2005
2010
2015
2020
0
1
2
3
4
5
6
7
2
1
1
1
3
1
1
1
1
1
1
1
1
2
1
2
4
1
1
2
1
2
2
1
1
1
2
4
3
1
1
2
3
6
1
1
2
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on scopus.com
-
on orcid.org
On csauthors.net:
Bibliography
2024
Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
Hardware implementations, SCA/FIA attacks, and countermeasures for the ASCON AEAD cipher: a review.
Proceedings of the 39th Conference on Design of Circuits and Integrated Systems, 2024
Electromagnetic Fault Injection Attack Methodology against AES Hardware Implementation.
Proceedings of the 39th Conference on Design of Circuits and Integrated Systems, 2024
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024
2023
A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
2022
IEEE Embed. Syst. Lett., 2022
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.
IEEE Access, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
2020
Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies.
ACM J. Emerg. Technol. Comput. Syst., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks.
Int. J. Circuit Theory Appl., 2019
2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview.
Int. J. Circuit Theory Appl., 2017
Int. J. Circuit Theory Appl., 2017
2016
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions.
Int. J. Circuit Theory Appl., 2016
Secure cryptographic hardware implementation issues for high-performance applications.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Conference on Industrial Technology, 2015
2014
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
2012
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors.
IEEE J. Solid State Circuits, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
2010
Optimization of clock-gating structures for low-leakage high-performance applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking.
IEEE Trans. Neural Networks, 2009
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
2008
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing.
IEEE Trans. Neural Networks, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEEE J. Solid State Circuits, 2005
J. Low Power Electron., 2005
Proceedings of the Advances in Neural Information Processing Systems 18 [Neural Information Processing Systems, 2005
2003
Proceedings of the Integrated Circuit and System Design, 2003
2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Proceedings of the Integrated Circuit Design, 2000
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits.
Proceedings of the Integrated Circuit Design, 2000
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.
Proceedings of the Integrated Circuit Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 Design, 2000
1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1995
IEEE J. Solid State Circuits, July, 1995
IEEE Trans. Computers, 1995
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995
1993
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the European Design Automation Conference 1993, 1993