Antonio García
Orcid: 0000-0003-3533-4660Affiliations:
- University of Granada, Granada, Spain
According to our database1,
Antonio García
authored at least 52 papers
between 1998 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on orcid.org
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on senna.ugr.es
On csauthors.net:
Bibliography
2024
Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces.
Sensors, February, 2024
2023
Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications.
Cryptogr., June, 2023
2022
Table-Free Seed Generation for Hardware Newton-Raphson Square Root and Inverse Square Root Implementations in IoT Devices.
IEEE Internet Things J., 2022
2021
Intelligent Systems Reference Library 201, Springer, ISBN: 978-3-030-67265-2, 2021
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
2020
Cost-Effective Printed Electrodes Based on Emerging Materials Applied to Biosignal Acquisition.
IEEE Access, 2020
Privacy-enabled system based on Elliptic Curve Cryptography to reduce risks of contagion in pandemics.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
2019
Elliptic Curve Cryptography hardware accelerator for high-performance secure servers.
J. Supercomput., 2019
Wearable System for Biosignal Acquisition and Monitoring Based on Reconfigurable Technologies.
Sensors, 2019
Efficient Elliptic Curve Cryptoprocessor for enabling TLS protocol in low-cost reconfigurable SoCs.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019
2018
Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks.
Sensors, 2018
2017
Proceedings of the Bioinformatics and Biomedical Engineering, 2017
2016
Microprocess. Microsystems, 2016
2015
Improvements for the applicability of power-watermarking to embedded IP cores protection: e-coreIPP.
Digit. Signal Process., 2015
2013
Noise Suppression in ECG Signals through Efficient One-Step Wavelet Processing Techniques.
J. Appl. Math., 2013
Digit. Signal Process., 2013
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2013
2012
Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology.
Microprocess. Microsystems, 2012
A reconstruction method for electrical capacitance tomography based on image fusion techniques.
Digit. Signal Process., 2012
Quantization analysis and enhancement of a VLSI gradient-based motion estimation architecture.
Digit. Signal Process., 2012
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Improved gradient-based motion estimation on reconfigurable platforms.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
2008
Int. J. Reconfigurable Comput., 2008
Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.
Proceedings of the FPL 2008, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the FPL 2007, 2007
Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.
Proceedings of the FPL 2007, 2007
2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
2005
J. Circuits Syst. Comput., 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the Field Programmable Logic and Application, 2004
2003
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies.
J. VLSI Signal Process., 2003
Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic.
J. VLSI Signal Process., 2003
A Fast QRNS-Based Algorithm for the DCT and Its Field-Programmable Logic Implementation.
J. Circuits Syst. Comput., 2003
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation.
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
2001
J. VLSI Signal Process., 2001
Implementation of the one dimensional discrete cosine transform using the residue number system.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
2000
A new architecture to compute the discrete cosine transform using the quadratic residue number system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform.
Proceedings of the Field-Programmable Logic and Applications, 2000
An efficient RNS architecture for the computation of discrete wavelet transforms on programmable devices.
Proceedings of the 10th European Signal Processing Conference, 2000
1999
RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Pipelined Hogenauer CIC filters using field-programmable logic and residue number system.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998