António Canelas
Orcid: 0000-0002-9414-742X
According to our database1,
António Canelas
authored at least 36 papers
between 2012 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2022
A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs.
IEEE Access, 2021
2020
A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
FUZYE: A Fuzzy <i>c</i>-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications.
Microelectron. J., 2020
Integr., 2020
2019
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing.
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
2018
Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.
Integr., 2018
Expert Syst. Appl., 2018
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 15th International Conference on Synthesis, 2018
2017
Integr., 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks.
Proceedings of the 14th International Conference on Synthesis, 2017
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization.
Proceedings of the 14th International Conference on Synthesis, 2017
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer.
Integr., 2016
Integr., 2016
Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations.
Proceedings of the 13th International Conference on Synthesis, 2016
On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies.
Proceedings of the 13th International Conference on Synthesis, 2016
2015
Integr., 2015
Extraction and application of wiring symmetry rules to route analog multiport terminals.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Integr., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
A SAX-GA approach to evolve investment strategies on financial markets based on pattern discovery techniques.
Expert Syst. Appl., 2013
Multi-dimensional pattern discovery in financial time series using sax-ga with extended robustness.
Proceedings of the Genetic and Evolutionary Computation Conference, 2013
Multi-port multi-terminal analog router based on an evolutionary optimization kernel.
Proceedings of the IEEE Congress on Evolutionary Computation, 2013
2012
Proceedings of the Genetic and Evolutionary Computation Conference, 2012