Antoni Portero

Orcid: 0000-0003-1319-6404

According to our database1, Antoni Portero authored at least 31 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

Online presence:

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Bibliography

2024
Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation.
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

Data Prefetching on Processors with Heterogeneous Memory.
Proceedings of the International Symposium on Memory Systems, 2024

Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC.
Proceedings of the Architecture of Computing Systems - 37th International Conference, 2024

2023
NoC-based hardware software co-design framework for dataflow thread management.
J. Supercomput., November, 2023

COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores.
Proceedings of the Architecture of Computing Systems - 36th International Conference, 2023

2021

2019
Comprehensive Characterization of an Open Source Document Search Engine.
ACM Trans. Archit. Code Optim., 2019

2018
Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud.
Sensors, 2018

Impact of Address Generation on Multimedia Embedded VLIW Processors.
Proceedings of the Computer Information Systems and Industrial Management, 2018

2017
A Web-Based Modelling and Monitoring System Based on Coupling Environmental Models and Hydrological-Related Data.
J. Commun., 2017

A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application.
CoRR, 2017

Efficient Data-Driven Task Allocation for Future Many-Cluster On-chip Systems.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

Just-In-Time Execution Through On-Demand Resource Allocation in HPC Systems.
Proceedings of the International Conference on Algorithms, Computing and Systems, Jeju Island, Republic of Korea, August 10, 2017


A Scalable and Low-Power FPGA-Aware Network-on-Chip Architecture.
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2017

2016
Software defined Network-on-Chip for scalable CMPs.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Using an adaptive and time predictable runtime system for power-aware HPC-oriented applications.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

2015
Precision-Aware application execution for Energy-optimization in HPC node system.
CoRR, 2015

Simulation of a runoff model running with multi-criteria in a cluster system.
Proceedings of the Conference on Summer Computer Simulation, 2015

HARPA: Solutions for dependable performance under physically induced performance variability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Flood Prediction Model Simulation With Heterogeneous Trade-Offs In High Performance Computing Framework.
Proceedings of the 29th European Conference on Modelling and Simulation, 2015

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Harnessing Performance Variability: A HPC-Oriented Application Scenario.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Enhancing an x86_64 multi-core architecture with data-flow execution support.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
System and Application Scenarios for Disaster Management Processes, the Rainfall-Runoff Model Case Study.
Proceedings of the Computer Information Systems and Industrial Management, 2014

2012
Simulating the future kilo-x86-64 core processors and their infrastructure.
Proceedings of the 2012 Spring Simulation Multiconference, 2012

2011
Methodology for Energy-Flexibility Space Exploration and Mapping of Multimedia Applications to Single-Processor Platform Styles.
IEEE Trans. Circuits Syst. Video Technol., 2011

TERAFLUX: Exploiting Tera-device Computing Challenges.
Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011

2006
Energy-Aware MPEG-4 Single Profile in HW-SW Multi-Platform Implementation.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Hardware Synthesis of Parallel Machines from SystemC.
Proceedings of the Forum on specification and Design Languages, 2005


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