Anthony S. Wojcik

According to our database1, Anthony S. Wojcik authored at least 22 papers between 1971 and 2001.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2001
Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000
Candidate subcircuits for functional module identification in logic circuits.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
An Application of Formal Analysis to Software in a Fault-Tolerant Environment.
IEEE Trans. Computers, 1999

Design Recovery for Incomplete Combinational Logic.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
Identifying High-Level Components in Combinational Circuits.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1991
Reasoning About Digital Systems.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

1989
Formal Verification of Fault Tolerance Using Theorem-Proving Techniques.
IEEE Trans. Computers, 1989

A General, Constructive Approach to Fault-Tolerant Design Using Redundancy.
IEEE Trans. Computers, 1989

An Automated Reasoning Problem Associated with Proving Claims about Programs Using Floyd-Hoare Inductive Assertin Methods.
J. Autom. Reason., 1989

1988
Modular Decomposition of Combinational Multiple-Valued Circuits.
IEEE Trans. Computers, 1988

1987
A Rule-Based Circuit Representation for Automated CMOS Design and Verification.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
An Artificial Intelligence Based Implementation of the P-Algorithm for Test Generation.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
Automated Synthesis of Combinational Logic Using Theorem-Proving Techniques.
IEEE Trans. Computers, 1985

1984
A formal design verification system based on an automated reasoning system.
Proceedings of the 21st Design Automation Conference, 1984

1983
Automated Design of Multiple-Valued Logic Circuits by Automatic Theorem Proving Techniques.
IEEE Trans. Computers, 1983

Formal design verification of digital systems.
Proceedings of the 20th Design Automation Conference, 1983

1981
On the Design of 4-Valued Digital Systems.
IEEE Trans. Computers, 1981

1980
On the Design of Three-Valued Asynchronous Modules.
IEEE Trans. Computers, 1980

1978
Parallel and serial decompositions of multi-valued sequential machines.
Proceedings of the eighth international symposium on Multiple-valued logic, 1978

1974
An Analysis of Some Relationships Between Post and Boolean Algebras.
J. ACM, 1974

1971
Relationships Between Post and Boolean Algebras With Application to Multi-Valued Switching Theory
PhD thesis, 1971

On the Cost of Base N Adders.
IEEE Trans. Computers, 1971


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