Anthony P. Ambler

Affiliations:
  • The University of Texas, Department of Electrical and Computer Engineering, Austin, TX, USA
  • Brunel University, Uxbridge, Middlesex, UK


According to our database1, Anthony P. Ambler authored at least 24 papers between 1984 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1998, "For contributions to economics of testing complex digital devices and systems.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
A HW/SW Co-design Methodology: An Accurate Power Efficiency Model and Design Metrics for Embedded System.
Proceedings of the 10th ACIS International Conference on Software Engineering, 2009

2006
Behavioral Test Economics.
Proceedings of the 2006 IEEE International Test Conference, 2006

Design Trade-Offs and Power Reduction Techniques for High Performance Circuits and System.
Proceedings of the Computational Science and Its Applications, 2006

2005
Reduction of Power and Test Time by Removing Cluster of Don't-Care from Test Data Set.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2002
System Manufacturing Test Cost Model.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Is It Rocket Science?
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
From DFT to systems test - a model based cost optimization tool.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

1997
The Economics of System-Level Testing.
IEEE Des. Test Comput., 1997

1995
Cost-Effective System-Level Test Strategies.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
Sensitivity analysis in economics based test strategy planning.
J. Electron. Test., 1994

Test strategy planning using economic analysis.
J. Electron. Test., 1994

System Test Cost Modelling Based on Event Rate Analysis.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993
The application and use of boundary scan: Bleeker, H, van den Eijnden, P and de Jong, FBoundary-scan test - a practical approach Kluwer Academic (1992) ISBN 0 7923 9296 5, £50.75, pp 222.
Microprocess. Microsystems, 1993

Economics Modelling for the Determination of Test Strategies for Complex VLSI Boards.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Algorithms for Cost Optimised Test Strategy Selection.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Economics in Design and Test.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
A Steady-State Response Test Generation for Mixed-Signal Integrated Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Economic Effects in Design and Test.
IEEE Des. Test Comput., 1991

1989
Cost Analysis of Test Method Environments.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
Estimation of area and performance overheads for testable VLSI circuits.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1986
Economically Viable Automatic Insertion of Self-Test Features for Custom VLSI.
Proceedings of the Proceedings International Test Conference 1986, 1986

1984
An Analysis of the Economics of Self Test.
Proceedings of the Proceedings International Test Conference 1984, 1984

Ultimate: A hardware logic simulation engine.
Proceedings of the 21st Design Automation Conference, 1984


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