Anshuman Chandra

According to our database, Anshuman Chandra authored at least 45 papers between 2000 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard.

Sandeep Kumar Goel, Ankita Patidar, Moiz Khan, Frank Lee, Anshuman Chandra, Martin Keim, Naim Lemar, Jonathan Gaudet, Quoc Phan, Vidya Neerkundar

Proceedings of the IEEE International Test Conference, 2024

New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405.

Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra

Proceedings of the IEEE European Test Symposium, 2024

2023

A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation.

Anshuman Chandra, Moiz Khan, Ankita Patidar, Fumiaki Takashima, Sandeep Kumar Goel, Bharath Shankaranarayanan, Vuong Nguyen, Vistrita Tyagi, Manish Arora

Proceedings of the IEEE International Test Conference, 2023

2015

Designing efficient combinational compression architecture for testing industrial circuits.

Anshuman Chandra, Santosh Kulkarni, Subramanian Chebiyam, Rohit Kapur

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Designing effective scan compression solutions for industrial circuits.

Subramanian Chebiyam, Anshuman Chandra, Rohit Kapur

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

Unifying scan compression.

Swapnil Bahl, Shreyans Rungta, Shray Khullar, Rohit Kapur, Anshuman Chandra, Salvatore Talluto, Pramod Notiyath, Ajay Rajagopalan

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A Case Study on Implementing Compressed DFT Architecture.

Anshuman Chandra, Subramanian Chebiyam, Rohit Kapur

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Special session 11B: Hot topic on-chip clocking - Industrial trends.

Anshuman Chandra

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2011

Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C).

Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur

Proceedings of the 20th IEEE Asian Test Symposium, 2011

3D-Scalable Adaptive Scan (3D-SAS).

Uzair Shah Syed, Krishnendu Chakrabarty, Anshuman Chandra, Rohit Kapur

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2009

Proactive management of X's in scan chains for compression.

Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Scalable Adaptive Scan (SAS).

Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Bounded Adjacent Fill for Low Capture Power Scan Testing.

Anshuman Chandra, Rohit Kapur

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Interval Based X-Masking for Scan Compression Architectures.

Anshuman Chandra, Rohit Kapur

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction.

Anshuman Chandra, Felix Ng, Rohit Kapur

Proceedings of the Design, Automation and Test in Europe, 2008

Not All Xs are Bad for Scan Compression.

Anshuman Chandra, Rohit Kapur

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.

Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra

IEEE Trans. Very Large Scale Integr. Syst., 2007

DFT MAX and Power.

Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri

J. Low Power Electron., 2007

Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction.

Anshuman Chandra, Haihua Yan, Rohit Kapur

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2006

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes.

Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra

IEEE Trans. Instrum. Meas., 2006

Response compaction for system-on-a-chip based on advanced convolutional codes.

Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra

Sci. China Ser. F Inf. Sci., 2006

2005

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.

Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra

J. Comput. Sci. Technol., 2005

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.

Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen

IEICE Trans. Inf. Syst., 2005

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.

Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes.

Anshuman Chandra, Krishnendu Chakrabarty

J. Electron. Test., 2004

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.

Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Rapid and Energy-Efficient Testing for Embedded Cores.

Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A unified approach to reduce SOC test data volume, scan power and testing time.

Anshuman Chandra, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes.

Anshuman Chandra, Krishnendu Chakrabarty

IEEE Trans. Computers, 2003

A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design.

Vikram Iyengar, Anshuman Chandra

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization.

Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty

Proceedings of the 2003 Design, 2003

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.

Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Test data compression and decompression based on internal scanchains and Golomb coding.

Anshuman Chandra, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Low-power scan testing and test data compression forsystem-on-a-chip.

Anshuman Chandra, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

How Effective are Compression Codes for Reducing Test Data Volume?

Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression.

Anshuman Chandra, Krishnendu Chakrabarty

Proceedings of the 2002 Design, 2002

Reduction of SOC test data volume, scan power and testing time using alternating run-length codes.

Anshuman Chandra, Krishnendu Chakrabarty

Proceedings of the 39th Design Automation Conference, 2002

Test Resource Partitioning for System-on-a-Chip.

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra

Frontiers in electronic testing 20, Kluwer / Springer, ISBN: 978-1-4020-7119-5, 2002

2001

Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters.

Anshuman Chandra, Krishnendu Chakrabarty, Mark C. Hansen

VLSI Design, 2001

System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes.

Anshuman Chandra, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Test Resource Partitioning for SOCs.

Anshuman Chandra, Krishnendu Chakrabarty

IEEE Des. Test Comput., 2001

Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression.

Anshuman Chandra, Krishnendu Chakrabarty

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding.

Anshuman Chandra, Krishnendu Chakrabarty

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip.

Anshuman Chandra, Krishnendu Chakrabarty

Proceedings of the 38th Design Automation Conference, 2001

2000

Test Data Compression for System-on-a-Chip Using Golomb Codes.

Anshuman Chandra, Krishnendu Chakrabarty

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000