Anran Yin

According to our database, Anran Yin authored at least 4 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 22-nm 264-GOPS/mm² 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs.

Feiran Liu, Anran Yin, Chen Xue, Bo Wang, Zhongyuan Feng, Han Liu, Xiang Li, Hui Gao, Tianzhu Xiong, Xin Si

IEEE Trans. Very Large Scale Integr. Syst., December, 2024

A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree.

Xin Si, Fangyuan Dong, Shengnan He, Yuhui Shi, Anran Yin, Hui Gao, Xiang Li

IEEE Trans. Very Large Scale Integr. Syst., November, 2024

2023

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks.

Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation.

Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022