Anoop Narayan Bhat

Orcid: 0000-0003-1247-3457

According to our database1, Anoop Narayan Bhat authored at least 6 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
23.5 A 7.6mW IR-UWB Receiver Achieving -13dBm Blocker Resilience with a Linear RF Front-End.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
An 8.7 mW/TX, 21 mW/RX 6-to-9GHz IEEE 802.15.4a/4z Compliant IR-UWB Transceiver with Pulse Pre-Emphasis achieving 14mm Ranging Precision.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving <sub>p-p</sub> Output Swing Over 0.01-5.4-GHz for Direct RF Sampling Applications.
IEEE J. Solid State Circuits, 2022

2021
A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications.
IEEE J. Solid State Circuits, 2021

2019
Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2017
25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017


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