Anoop Bhagyanath
Orcid: 0000-0001-7866-5983
According to our database1,
Anoop Bhagyanath
authored at least 16 papers
between 2015 and 2023.
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Bibliography
2023
Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann Architectures.
ACM Trans. Embed. Comput. Syst., September, 2023
Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann Architectures.
Proceedings of the 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2023
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2023
Proceedings of the 47th IEEE Annual Computers, Software, and Applications Conference, 2023
2022
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2022
Code generation criteria for buffered exposed datapath architectures from dataflow graphs.
Proceedings of the LCTES '22: 23rd ACM SIGPLAN/SIGBED International Conference on Languages, 2022
2021
PhD thesis, 2021
2018
Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP.
Theory Pract. Log. Program., 2018
On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units.
Proceedings of the 18th International Conference on Application of Concurrency to System Design, 2018
2017
Exploring different execution paradigms in exposed datapath architectures with buffered processing units.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units.
Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017
2016
The selector-tree network: A new self-routing and non-blocking interconnection network.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
Optimal compilation for exposed datapath architectures with buffered processing units by SAT solvers.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016
Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) Architectures.
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016
2015
Proceedings of the 2015 IEEE Real-Time Systems Symposium, 2015