Annalisa Massini
Orcid: 0000-0001-8343-8929
According to our database1,
Annalisa Massini
authored at least 53 papers
between 1993 and 2024.
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Bibliography
2024
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024
2023
IEEE/ACM Trans. Netw., April, 2023
Realizing Optimal All-to-All Personalized Communication Using Butterfly-Based Networks.
IEEE Access, 2023
2022
Proceedings of the 30th International Conference on Software, 2022
2021
J. Log. Algebraic Methods Program., 2021
CoRR, 2021
IEEE Access, 2021
A Constraint Optimization-Based Sense and Response System for Interactive Business Performance Management.
Appl. Artif. Intell., 2021
Proceedings of the International Conference on Software, 2021
Proceedings of the 40th IEEE Conference on Computer Communications, 2021
Efficiently Parallelizable Strassen-Based Multiplication of a Matrix by its Transpose.
Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021
2020
IEEE/ACM Trans. Netw., 2020
Inf., 2020
Optimal all-to-all personalized communication on Butterfly networks through a reduced Latin square.
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020
2019
CoRR, 2019
Proceedings of the Parallel Processing and Applied Mathematics, 2019
Generating T1DM Virtual Patients for In Silico Clinical Trials via AI-Guided Statistical Model Checking.
Proceedings of the Joint Proceedings of the RCRA International Workshop and of the RCRA Incontri e Confronti Workshop co-located with the 18th International Conference of the Italian Association for Artificial Intelligence (AIIA 2019), 2019
Proceedings of the 1st Workshop on Artificial Intelligence and Formal Verification, 2019
2018
Proceedings of the Workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion co-located with the Federated Logic Conference, 2018
2017
2016
Anytime system level verification via parallel random exhaustive hardware in the loop simulation.
Microprocess. Microsystems, 2016
2015
Proceedings of the Proceedings Sixth International Symposium on Games, 2015
Proceedings of the Bioinformatics and Biomedical Engineering, 2015
2014
System Level Formal Verification via Distributed Multi-core Hardware in the Loop Simulation.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Proceedings of the Formal Methods in Computer-Aided Design, 2014
Anytime System Level Verification via Random Exhaustive Hardware in the Loop Simulation.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Proceedings of the Computer Aided Verification - 25th International Conference, 2013
2012
Wirel. Networks, 2012
High Performance Parallelization of COMPSYN on a Cluster of Multicore Processors with GPUs.
Proceedings of the International Conference on Computational Science, 2012
Accelerating the Production of Synthetic Seismograms by a Multicore Processor Cluster with Multiple GPUs.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
2011
On Adaptive Density Deployment to Mitigate the Sink-Hole Problem in Mobile Sensor Networks.
Mob. Networks Appl., 2011
2010
Wirel. Networks, 2010
2009
Variable Density Deployment and Topology Control for the Solution of the Sink-Hole Problem.
Proceedings of the Quality of Service in Heterogeneous Networks, 2009
Proceedings of the 12th International Symposium on Modeling Analysis and Simulation of Wireless and Mobile Systems, 2009
Proceedings of the 17th annual IEEE International Conference on Network Protocols, 2009
2008
Proceedings of the Self-Organizing Systems, Third International Workshop, 2008
Proceedings of the Distributed Computing in Sensor Systems, 2008
2006
2004
Efficient algorithms for checking the equivalence of multistage interconnection networks.
J. Parallel Distributed Comput., 2004
2003
Discret. Appl. Math., 2003
2001
Theor. Comput. Sci., 2001
2000
Telecommun. Syst., 2000
1999
1998
A virtually nonblocking self-routing permutation network which routes packets in \mathrm{O}(\log_{2} N) time.
Telecommun. Syst., 1998
1997
Proceedings of the Graph Drawing, 5th International Symposium, 1997
1995
An O(log<sub>2</sub> N) Depth Asymptotically Nonblocking Self-Routing Permutation Network.
IEEE Trans. Computers, 1995
1994
1993
A Quasi-Nonblocking Self-Routing Network which Routs Packets in log<sub>2</sub><i>N</i> Time.
Proceedings of the Proceedings IEEE INFOCOM '93, The Conference on Computer Communications, Twelfth Annual Joint Conference of the IEEE Computer and Communications Societies, Networking: Foundation for the Future, San Francisco, CA, USA, March 28, 1993