Annachiara Spagnolo

According to our database, Annachiara Spagnolo authored at least 9 papers between 2013 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A 1^st Order Incremental Sigma-Delta with Refined Digitally Implemented Feed-Forward for 2-stage ADC.

Toshio Yasue, Fortunato Frazzica, Annachiara Spagnolo, David San Segundo Bello, Maarten De Bock, Piet Wambacq, Jan Craninckx

Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020

2018

An Adaptive Frame Image Sensor with Fine-Grained Power Management for Ultra-Low Power Internet of Things Application.

Masato Osawa, S. Hiraide, S. Suzuki, H. Kato, Kosei Tamiya, Yasunari Harada, Kuba Raczkowski, J. L. Bacq, Peter Van Wesemael, M. Liu, Annachiara Spagnolo, K. De Munck, S. Guerrieri, Jonathan Borremans

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017

A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS.

Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, Ilja Ocket, André Bourdoux, Piet Wambacq, Jan Craninckx, Wim Van Thillo

IEEE J. Solid State Circuits, 2017

2016

A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS.

Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, André Bourdoux, Piet Wambacq, Wim Van Thillo

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

High-speed analog-to-digital converters in downscaled CMOS.

Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

A 7.65-mW 5-bit 90-nm 1-Gs/s Folded Interpolated ADC Without Calibration.

Stefano D'Amico, Giuseppe Cocciolo, Annachiara Spagnolo, Marcello De Matteis, Andrea Baschirotto

IEEE Trans. Instrum. Meas., 2014

A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS.

Annachiara Spagnolo, Bob Verbruggen, Piet Wambacq, Stefano D'Amico

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS.

Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq

Proceedings of the ESSCIRC 2014, 2014

2013

CMOS low-power transceivers for 60GHz multi Gbit/s communications.

Vojkan Vidojkovic, Viki Szortyka, Khaled Khalaf, Giovanni Mangraviti, Bertrand Parvais, Kristof Vaesen, Steven Brebels, Annachiara Spagnolo, Michael Libois, John R. Long, Kuba Raczkowski, Praveen Raghavan, André Bourdoux, Min Li, Charlotte Soens, Vito Giannini, Piet Wambacq

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013