Anna Antola

A. Lorenzo Mezzalira

Manuel Roveri

Proceedings of the 2014 IEEE International Symposium on Robotic and Sensors Environments, 2014

2007

Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseC.

[BibT_eX]

Marco Castagna

Pamela Gotti

Marco D. Santambrogio

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2002

On-line Diagnosis and Reconfiguration of FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

Semiconcurrent Error Detection in Data Paths.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

2000

Dedicated Circuits for the Generation of Windows in Image Processing Architectures.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2000

1998

High-level Synthesis of Data Paths with Concurrent Error Detection.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

Semi-Concurrent Error Detection in Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996

A chip-set for the Generalized Hough Transform.

[BibT_eX]

[DOI]

Maria Grazia Albanesi

Marco Ferretti

Roberto M. Negrini

J. VLSI Signal Process., 1996

A high-level synthesis approach to optimum design of self-checking circuits.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

Optimizing High-Level Synthesis for Self-Checking Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Balancing of Fault Tolerance in the New Version of the FERMI Channel Chip: a Functional Evaluation.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

A model for the evaluation of fault tolerance in the FERMI system.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994

High level architectural synthesis: Precedence analysis and automatic cycle detection in data flow graphs.

[BibT_eX]

[DOI]

Fausto Distante

Andrea Marchese

Microprocess. Microprogramming, 1994

1993

Modular design methodologies for image processing architectures.

[BibT_eX]

[DOI]

Alberto Avai

IEEE Trans. Very Large Scale Integr. Syst., 1993

High level synthesis through folding of data flow graphs: Optimal intra-node scheduling.

[BibT_eX]

[DOI]

Fausto Distante

Andrea Marchese

Microprocess. Microprogramming, 1993

Modular Design Methodologies for Image Processing Architectures.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

Fault tolerance in FFT arrays: Time redundancy approaches.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1992

Window-based dedicated parallel architectures for image processing.

[BibT_eX]

[DOI]

Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992

1991

Testing and diagnosis of<i>FFT</i> arrays.

[BibT_eX]

[DOI]

Donatella Sciuto

J. VLSI Signal Process., 1991

Definition and evaluation of a transputer-based architecture for image compression and reconstruction.

[BibT_eX]

[DOI]

M. Tellarini

Microprocessing and Microprogramming, 1991

DFG: a graph based approach for algorithmic flow driven architecture synthesis.

[BibT_eX]

[DOI]

Fausto Distante

Microprocessing and Microprogramming, 1991

1990

Reconfiguration of FFT arrays: a flow-driven approach.

[BibT_eX]

[DOI]

Nello Scarabottolo

Proceedings of the Application Specific Array Processors, 1990

1988

Evaluation of complexity for different layouts of butterfly networks.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1988

Multiple-transform pipelines for image coding.

[BibT_eX]

[DOI]