Ann Gordon-Ross

Int. J. Circuit Theory Appl., 2021

2019

Machine Learning-based Prediction for Dynamic, Runtime Architectural Optimizations of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Machine Learning-based Prediction for Phase-Based Dynamic Architectural Specialization.

[BibT_eX]

[DOI]

Islam Badreldin

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

PCS: A Productive Computational Science Platform.

[BibT_eX]

[DOI]

Kirstin Kleese van Dam

Seyong Lee

Thorsten Kurth

Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

Energy Prediction for Cache Tuning in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Machine Learning-based Prediction for Dynamic Architectural Optimizations.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

Accelerating Scientific Discovery with SCAIGATE Science Gateway.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on eScience, 2019

Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2018

PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A comparison-free sorting algorithm on CPUs and GPUs.

[BibT_eX]

[DOI]

Samer Abubaker

J. Supercomput., 2018

Microprocessor Optimizations for the Internet of Things: A Survey.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems.

[BibT_eX]

[DOI]

Comput., 2018

Low Effort Design Space Exploration Methodology for Configurable Caches.

[BibT_eX]

[DOI]

Comput., 2018

<i>TaPT</i>: Temperature-Aware Dynamic Cache Optimization for Embedded Systems.

[BibT_eX]

[DOI]

Comput., 2018

Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges.

[BibT_eX]

[DOI]

Islam Badreldin

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

An Efficient O(N) Comparison-Free Sorting Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Optimizing FPGA Performance, Power, and Dependability with Linear Programming.

[BibT_eX]

[DOI]

Nicholas Wulf

ACM Trans. Reconfigurable Technol. Syst., 2017

Accelerating High-energy Physics Exploration with Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the Practice and Experience in Advanced Research Computing 2017: Sustainability, 2017

Overlay-based side-channel countermeasures: A case study on correlated noise generation.

[BibT_eX]

[DOI]

Austin Baylis

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016

A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace Computing.

[BibT_eX]

[DOI]

Nicholas Wulf

ACM Trans. Reconfigurable Technol. Syst., 2016

MACS: A Highly Customizable Low-Latency Communication Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

CaPPS: cache partitioning with partial sharing for multi-core embedded systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2016

Microprocessor Optimizations for the Internet of Things.

[BibT_eX]

[DOI]

CoRR, 2016

Temperature-aware Dynamic Optimization of Embedded Systems.

[BibT_eX]

[DOI]

CoRR, 2016

Postponing wearout failures in chip multiprocessors using thermal management and thread migration.

[BibT_eX]

[DOI]

Elham Kashefi

Hamid R. Zarandi

Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Shaon Yousuf

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Phase-Based Dynamic Instruction Window Optimization for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded Devices.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Configuration prefetching and reuse for preemptive hardware multitasking on partially reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Modeling and Analysis of Fault Detection and Fault Tolerance in Wireless Sensor Networks.

[BibT_eX]

[DOI]

Joseph Antoon

ACM Trans. Embed. Comput. Syst., 2015

Application-Specific Customization of Dynamic Profiling Mechanisms for Sensor Networks.

[BibT_eX]

[DOI]

IEEE Access, 2015

Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

An Automated High-Level Design Framework for Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Phase-based Cache Locking for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Multi-Core Embedded Wireless Sensor Networks: Architecture and Applications.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Multibit Fault Injection for Field-Programmable Gate Arrays with Simple, Portable Fault Injector.

[BibT_eX]

[DOI]

J. Aerosp. Inf. Syst., 2014

Phase distance mapping: a phase-based cache tuning methodology for embedded systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2014

Dynamic Phase-Based Optimization of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Analysis of cache tuner architectural layouts for multicore embedded systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

Thermal-aware phase-based tuning of embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Minimum Effort Design Space Subsetting for Configurable Caches.

[BibT_eX]

[DOI]

Pablo Viana

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Dynamic Scheduling for Reduced Energy in Configuration-Subsetted Heterogeneous Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013

Scalable Digital CMOS Comparator Using a Parallel Prefix Tree.

[BibT_eX]

[DOI]

Behrooz Parhami

IEEE Trans. Very Large Scale Integr. Syst., 2013

High-performance optimizations on tiled many-core embedded systems: a matrix multiplication case study.

[BibT_eX]

[DOI]

J. Supercomput., 2013

Adaptive loop caching using lightweight runtime control flow analysis.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Dynamic profiling and fuzzy-logic-based optimization of sensor network platforms.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

T-SPaCS - A Two-Level Single-Pass Cache Simulation Methodology.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

A Cache Tuning Heuristic for Multicore Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

A lightweight dynamic optimization methodology and application metrics estimation model for wireless sensor networks.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2013

A survey on cache tuning from a power/energy perspective.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2013

Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Accuracy-Guided Runtime Adaptive Profiling Optimization of Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference and Workshops on Engineering of Computer Based Systems, 2013

HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

Low-Energy Instruction Cache Optimization Techniques for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Reconfigurable Fault Tolerance: A Comprehensive Framework for Reliable and Adaptive FPGA-Based Space Computing.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2012

High-Performance Energy-Efficient Multicore Embedded Computing.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

An MDP-Based Dynamic Optimization Methodology for Wireless Sensor Networks.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

Dynamic Cache Reconfiguration for Soft Real-Time Systems.

[BibT_eX]

[DOI]

Weixun Wang

Prabhat Mishra

ACM Trans. Embed. Comput. Syst., 2012

Combining code reordering and cache configuration.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2012

ATLeS-SN.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2012

A double data rate 8T-cell SRAM architecture for systems-on-chip.

[BibT_eX]

[DOI]

Mohammad Shatnawi

Proceedings of the 2012 International Symposium on System on Chip, 2012

A single-pass cache simulation methodology for two-level unified caches.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

Parallelized benchmark-driven performance evaluation of SMPs and tiled multi-core architectures for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Performance Computing and Communications Conference, 2012

Dynamic phase-based tuning for embedded systems using phase distance mapping.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Online algorithms for wireless sensor networks dynamic optimization.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE Consumer Communications and Networking Conference (CCNC), 2012

An application classification guided cache tuning heuristic for multi-core architectures.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Shadow Dynamic Finite State Machine for Branch Prediction: An Alternative for the 2-bit Saturating Counter.

[BibT_eX]

[DOI]

Informatica (Slovenia), 2011

A Gigahertz Digital CMOS Divide-by-<i>N</i> Frequency Divider Based on a State Look-Ahead Structure.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2011

Topology design and performance analysis for networked earth observing small satellites.

[BibT_eX]

[DOI]

Proceedings of the MILCOM 2011, 2011

CPACT - The conditional parameter adjustment cache tuner for dual-core architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Markov Modeling of Fault-Tolerant Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of 20th International Conference on Computer Communications and Networks, 2011

Partially reconfigurable system-on-chips for adaptive fault tolerance.

[BibT_eX]

[DOI]

Shaon Yousuf

Adam Jacobs

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Formulation-level design space exploration for partially reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Hardware module reuse and runtime assembly for dynamic management of reconfigurable resources.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

On the interplay of loop caching, code compression, and cache configuration.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010

SIP-Based IMS Signaling Analysis for WiMax-3G Interworking Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Mob. Comput., 2010

Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2010

A lightweight dynamic optimization methodology for wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th International Conference on Wireless and Mobile Computing, 2010

Transaction-Level Modeling for Sensor Networks Using SystemC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Sensor Networks, 2010

Lightweight runtime control flow analysis for adaptive loop caching.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

DAPR: Design Automation for Partially Reconfigurable FPGAs.

[BibT_eX]

Shaon Yousuf

Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

VAPRES: A Customizable and Flexible Base Architecture for Partially Reconfigurable Systems.

[BibT_eX]

Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Fast Configurable-Cache Tuning With a Unified Second-Level Cache.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems.

[BibT_eX]

[DOI]

Weixun Wang

Prabhat Mishra

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

SIP-Based IMS Registration Analysis for WiMax-3G Interworking Architectures.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Networking and Services, 2009

Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks.

[BibT_eX]

[DOI]

Rafael García

Proceedings of the FCCM 2009, 2009

SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Bitstream relocation with local clock domains for partially reconfigurable FPGAs.

[BibT_eX]

[DOI]

Adam Flynn

Proceedings of the Design, Automation and Test in Europe, 2009

An MDP-based application oriented optimal policy for wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008

Real-time performance analysis of Adaptive Link Rate.

[BibT_eX]

[DOI]

Baoke Zhang

Karthik Sabhanatarajan

Proceedings of the LCN 2008, 2008

Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices.

[BibT_eX]

[DOI]

Karthik Sabhanatarajan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A resource efficient content inspection system for next generation Smart NICs.

[BibT_eX]

[DOI]

Karthik Sabhanatarajan

Proceedings of the 26th International Conference on Computer Design, 2008

A table-based method for single-pass cache optimization.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy.

[BibT_eX]

[DOI]

Jeremy Lau

Brad Calder

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Design Framework for Partial Run-Time FPGA Reconfiguration.

[BibT_eX]

Chris Conger

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2007

A one-shot configurable-cache tuner for improved energy and performance.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Self-Tuning Configurable Cache.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Configurable cache subsetting for fast cache tuning.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

A first look at the interplay of code reordering and configurable caches.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Automatic Tuning of Two-Level Caches to Embedded Applications.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Tuning Caches to Applications for Low-Energy Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003

Tiny instruction caches for low power embedded systems.

[BibT_eX]

[DOI]

Susan Cotterell

ACM Trans. Embed. Comput. Syst., 2003

Frequent loop detection using efficient non-intrusive on-chip hardware.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2003

2002

Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example.

[BibT_eX]

[DOI]

Susan Cotterell

IEEE Comput. Archit. Lett., 2002

Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

A self-optimizing embedded microprocessor using a loop table for low power.

[BibT_eX]

[DOI]