Anmol Mathur

Orcid: 0000-0002-1704-462X

According to our database1, Anmol Mathur authored at least 22 papers between 1994 and 2022.

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Bibliography

2022
Deep-Learning Based Beam Selection Technique for 6G Millimeter Wave Communication.
Proceedings of the 2022 IEEE 33rd Annual International Symposium on Personal, 2022

2012
Low-Power Design Using the Si2 Common Power Format.
IEEE Des. Test Comput., 2012

2009
Functional Equivalence Verification Tools in High-Level Synthesis Flows.
IEEE Des. Test Comput., 2009

Power Reduction Techniques and Flows at RTL and System Level.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Non-cycle-accurate sequential equivalence checking.
Proceedings of the 46th Design Automation Conference, 2009

2007
Design for Verification in System-level Models and RTL.
Proceedings of the 44th Design Automation Conference, 2007

2006
Sequential Equivalence Checking.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
Embedded tutorial: formal equivalence checking between system-level models and RTL.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2003
Graph Transformations for Improved Tree Height Reduction.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2001
Improved Merging of Datapath Operators using Information Content and Required Precision Analysis.
Proceedings of the 38th Design Automation Conference, 2001

1998
Rate analysis for embedded systems.
ACM Trans. Design Autom. Electr. Syst., 1998

Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.
ACM Trans. Design Autom. Electr. Syst., 1998

Efficient equivalence checking of multi-phase designs using retiming.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

An Implicit Algorithm for Finding Steady States and its Application to FSM Verification.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Timing-driven placement for regular architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

RATAN: A tool for rate analysis and rate constraint debugging for embedded systems.
Proceedings of the European Design and Test Conference, 1997

An Efficient Assertion Checker for Combinational Properties.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Generalized Kraft's Inequality and Discrete <i>k</i>-Modal Search.
SIAM J. Comput., 1996

Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Re-engineering of timing constrained placements for regular architectures.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994
Compression-relaxation: a new approach to performance driven placement for regular architectures.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994


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