Ankit Wagle

According to our database1, Ankit Wagle authored at least 11 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

2023
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

2022
A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
CIDAN: Computing in DRAM with Artificial Neurons.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020
A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
Threshold Logic in a Flash.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018


  Loading...