Ankit More

Orcid: 0009-0004-2813-3988

According to our database1, Ankit More authored at least 25 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Microscaling Data Formats for Deep Learning.
CoRR, 2023

Shared Microexponents: A Little Shifting Goes a Long Way.
CoRR, 2023


2020
PIUMA: Programmable Integrated Unified Memory Architecture.
CoRR, 2020

2019
Application Performance Prediction and Optimization Under Cache Allocation Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Vertical Arbitration-Free 3-D NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads.
ACM Trans. Archit. Code Optim., 2018

2017
Traleika Glacier: A hardware-software co-designed approach to exascale computing.
Parallel Comput., 2017

Wireless NoCs Using Directional and Substrate Propagation Antennas.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

P<sup>4</sup>: Phase-based power/performance prediction of heterogeneous systems via neural networks.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Energy aware routing of multi-level Network-on-Chip traffic.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Locality-Aware Network Utilization Balancing in NoCs.
ACM Trans. Design Autom. Electr. Syst., 2015

Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping.
Proceedings of the 28th International Conference on VLSI Design, 2015

Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

2014
Static thread mapping for NoCs via binary instrumentation traces.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2012
3-D Parasitic Modeling for Rotary Interconnects.
Proceedings of the 25th International Conference on VLSI Design, 2012

A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

A unified design methodology for a hybrid wireless 2-D NoC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Simulation based study of wireless RF interconnects for practical CMOs implementation.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Leakage current analysis for intra-chip wireless interconnects.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010


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