Ankit Kaul

According to our database, Ankit Kaul authored at least 9 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators.

Ankit Kaul, Madison Manley, James Read, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention.

Wantong Li, Madison Manley, James Read, Ankit Kaul, Muhannad S. Bakir, Shimeng Yu

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

Methodologies for Modeling and Optimization of 2.5-D and 3-D Integration Architectures for Compute-In-Memory Applications.

Ankit Kaul

PhD thesis, 2023

2022

A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect.

Yandong Luo, Sourav Dutta, Ankit Kaul, Sung Kyu Lim, Muhannad S. Bakir, Suman Datta, Shimeng Yu

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021

Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture.

Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, Sung Kyu Lim

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Electrical and Performance Benefits of Advanced Monolithic Cooling for 2.5D Heterogeneous ICs.

Sreejith Kochupurackal Rajan, Ankit Kaul, Gary S. May, Muhannad S. Bakir

Proceedings of the IEEE International 3D Systems Integration Conference, 2021

Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance.

Ankit Kaul, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir

Proceedings of the IEEE International 3D Systems Integration Conference, 2021

2020

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication.

Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury

Proceedings of the VLSI-SoC: Design Trends, 2020

A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration.

Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020