Anirudh Iyengar
According to our database1,
Anirudh Iyengar
authored at least 19 papers
between 2014 and 2023.
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Bibliography
2023
A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays.
CoRR, 2023
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Magnetic Tunnel Junction Reliability Assessment Under Process Variations and Activity Factors and Mitigation Techniques.
J. Low Power Electron., 2018
Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
ACM J. Emerg. Technol. Comput. Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
2014
Synergistic circuit and system design for energy-efficient and robust domain wall caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014