Anirudh Devgan

According to our database, Anirudh Devgan authored at least 57 papers between 1993 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2009

Accelerated design of analog, mixed-signal circuits in Titan.

Anirudh Devgan, Bülent Basaran, David Colleran, Mar Hershenson

Proceedings of the 2009 International Symposium on Physical Design, 2009

2008

Reinventing EDA with manycore processors.

Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou

Proceedings of the 45th Design Automation Conference, 2008

2007

A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits.

Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce.

Anand Ramalingam, Anirudh Devgan, David Z. Pan

J. Low Power Electron., 2007

2006

Analytical yield prediction considering leakage/performance correlation.

Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Robust analytical gate delay modeling for low voltage circuits.

Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Leakage and Leakage Sensitivity Computation for Combinational Circuits.

Emrah Acar, Anirudh Devgan, Sani R. Nassif

J. Low Power Electron., 2005

Modeling and Analysis of Parametric Yield under Power and Performance Constraints.

Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Anirudh Devgan

IEEE Des. Test Comput., 2005

Power Variability and Its Impact on Design.

Anirudh Devgan, Sani R. Nassif

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.

Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Design of sub-90nm Circuits and Design Methodologies.

Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Modeling and Design of Chip-Package Interface.

Anirudh Devgan, Luca Daniel, Byron Krauter, Lei He

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power grid voltage integrity verification.

Maha Nizam, Farid N. Najm, Anirudh Devgan

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Variability modeling and variability-aware design in deep submicron integrated circuits.

Florentin Dartu, Anirudh Devgan, Noel Menezes

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

An efficient algorithm for statistical minimization of total power under timing yield constraints.

Murari Mani, Anirudh Devgan, Michael Orshansky

Proceedings of the 42nd Design Automation Conference, 2005

Spatially distributed 3D circuit models.

Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter

Proceedings of the 42nd Design Automation Conference, 2005

Sleep transistor sizing using timing criticality and temporal currents.

Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Leakage power: trends, analysis and avoidance.

David T. Blaauw, Anirudh Devgan, Farid N. Najm

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Achieving continuous V_T performance in a dual V_T process.

Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees.

Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Closed-form delay and slew metrics made easy.

Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell.

Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Anirudh Devgan

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

Parametric yield estimation considering leakage variability.

Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester

Proceedings of the 41th Design Automation Conference, 2004

2003

Closed form expressions for extending step delay and slew metrics to ramp inputs.

Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan

Proceedings of the 2003 International Symposium on Physical Design, 2003

Full chip leakage estimation considering power supply and temperature variations.

Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Efficient techniques for gate leakage estimation.

Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Leakage and leakage sensitivity computation for combinational circuits.

Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics.

Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Block-based Static Timing Analysis with Uncertainty.

Anirudh Devgan, Chandramouli V. Kashyap

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Delay and slew metrics using the lognormal distribution.

Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan

Proceedings of the 40th Design Automation Conference, 2003

2002

Correction to "interconnect synthesis without wire tapering".

Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

PERI: a technique for extending delay and slew metrics to ramp inputs.

Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

2001

RC delay metrics for performance optimization.

Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Interconnect synthesis without wire tapering.

Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect.

Hao Ji, Anirudh Devgan, Wayne Wei-Ming Dai

Proceedings of ASP-DAC 2001, 2001

2000

Transient sensitivity computation in controlled explicit piecewiselinear simulation.

Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov, David W. Winston

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A two moment RC delay metric for performance optimization.

Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap

Proceedings of the 2000 International Symposium on Physical Design, 2000

An "Effective" Capacitance Based Delay Metric for RC Interconnect.

Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K.

Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

Buffer insertion for noise and delay optimization.

Charles J. Alpert, Anirudh Devgan, Stephen T. Quay

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Realizable reduction for RC interconnect circuits.

Anirudh Devgan, Peter R. O'Brien

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Is wire tapering worthwhile?

Charles J. Alpert, Anirudh Devgan, Stephen T. Quay

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Buffer Insertion with Accurate Gate and Interconnect Delay Computation.

Charles J. Alpert, Anirudh Devgan, Stephen T. Quay

Proceedings of the 36th Conference on Design Automation, 1999

1998

Simulation of coupling capacitances using matrix partitioning.

Tuyen V. Nguyen, Anirudh Devgan, Ali Sadigh

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation.

Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov

Proceedings of the 35th Conference on Design Automation, 1998

Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial).

Anirudh Devgan, Sandip Kundu

Proceedings of the ASP-DAC '98, 1998

1997

State transformation in event driven explicit simulation.

Tuyen V. Nguyen, Anirudh Devgan

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Timing analysis and optimization: from devices to systems (tutorial).

Anirudh Devgan, Leon Stok, Sandip Kundu

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Efficient coupled noise estimation for on-chip interconnects.

Anirudh Devgan

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Wire Segmenting for Improved Buffer Insertion.

Charles J. Alpert, Anirudh Devgan

Proceedings of the 34st Conference on Design Automation, 1997

1996

Transient simulation of integrated circuits in the charge-voltage plane.

Anirudh Devgan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Efficient simulation of interconnect and mixed analog-digital circuits in ACES.

Anirudh Devgan, Ronald A. Rohrer

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Accurate device modeling techniques for efficient timing simulation of integrated circuits.

Anirudh Devgan

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Efficient and accurate transient simulation in charge-voltage plane.

Anirudh Devgan

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Adaptively controlled explicit simulation.

Anirudh Devgan, Ronald A. Rohrer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993

ACES: A Transient Simulation Strategy for Integrated Circuits.

Anirudh Devgan, Ronald A. Rohrer

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Event driven adaptively controlled explicit simulation of integrated circuits.

Anirudh Devgan, Ronald A. Rohrer

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993