Anindya Sundar Dhar
Orcid: 0000-0001-5288-4715Affiliations:
- Indian Institute of Technology Kharagpur, India
According to our database1,
Anindya Sundar Dhar
authored at least 88 papers
between 1992 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
-
on iitkgp.ac.in
On csauthors.net:
Bibliography
2024
A Generalized Rearranged Coprime Array Configuration for Direction-of-Arrival Estimation with Increased Degrees of Freedom.
Circuits Syst. Signal Process., September, 2024
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
Unfolded Coprime Transformed Nested Arrays for Increased DOF and Negligible Mutual Coupling.
Circuits Syst. Signal Process., December, 2023
Circuits Syst. Signal Process., June, 2023
A Novel Translated Coprime Array Configuration for Moving Platform in Direction-of-Arrival Estimation.
Circuits Syst. Signal Process., April, 2023
Circuits Syst. Signal Process., March, 2023
2022
IEEE Trans. Emerg. Top. Comput., 2022
A Novel $k$-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom.
IEEE Signal Process. Lett., 2022
IEEE Signal Process. Lett., 2022
FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion.
J. Parallel Distributed Comput., 2022
Digit. Signal Process., 2022
2021
Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion.
ACM Trans. Design Autom. Electr. Syst., 2021
IEEE Signal Process. Lett., 2021
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support.
J. Parallel Distributed Comput., 2021
A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation.
Circuits Syst. Signal Process., 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
SIBAM - Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications.
IEEE Trans. Circuits Syst., 2020
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables.
J. Electron. Test., 2020
Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
2019
J. Signal Process. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Microelectron. J., 2019
Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies.
J. Parallel Distributed Comput., 2019
Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm.
IET Circuits Devices Syst., 2019
Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations.
J. Electron. Test., 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019
FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform.
J. Signal Process. Syst., 2018
Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Circuits Syst. Signal Process., 2018
CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation.
Circuits Syst. Signal Process., 2018
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Microelectron. J., 2017
Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs.
J. Cell. Autom., 2017
IET Circuits Devices Syst., 2017
CORDIC-based Hann windowed sliding DFT architecture for real-time spectrum analysis with bounded error-accumulation.
IET Circuits Devices Syst., 2017
IET Circuits Devices Syst., 2017
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations.
J. Electron. Test., 2017
Algorithm/Architecture Co-design of Proportionate-type LMS Adaptive Filters for Sparse System Identification.
CoRR, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs.
Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017
2016
Microelectron. Reliab., 2016
Erratum to: A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation.
J. Real Time Image Process., 2016
A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation.
J. Real Time Image Process., 2016
J. Circuits Syst. Comput., 2016
Circuits Syst. Signal Process., 2016
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
2015
Microelectron. Reliab., 2015
Circuits Syst. Signal Process., 2015
New triple-transistor based defect-tolerant systems for reliable digital architectures.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis.
J. Signal Process. Syst., 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
2013
J. Signal Process. Syst., 2013
2012
A Variable RF Carrier Modulation Scheme for Ultralow Power Wireless Body-Area Network.
IEEE Syst. J., 2012
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
2011
2010
Microprocess. Microsystems, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2008
High Throughput VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis.
J. Comput., 2008
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC.
IEEE Trans. Circuits Syst. II Express Briefs, 2005
Novel architecture for QAM modulator-demodulator and its generalization to multicarrier modulation.
Microprocess. Microsystems, 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
2004
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Sampled analog architecture for DCT and DST.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Digital controlled analog architecture for DCT and DST using capacitor switching.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2001
Signal Process., 2001
Microprocess. Microsystems, 2001
CORDIC realization of the transversal adaptive filter using a trigonometric LMS algorithm.
Proceedings of the IEEE International Conference on Acoustics, 2001
2000
Systolizing the adaptive decision feedback equalizer using a symbolic state space formulation.
Proceedings of the 10th European Signal Processing Conference, 2000
1992
Proceedings of the Fifth International Conference on VLSI Design, 1992