Animesh Datta
According to our database1,
Animesh Datta
authored at least 26 papers
between 2005 and 2024.
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Bibliography
2024
2022
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
2018
The von Neumann Theil index: characterizing graph centralization using the von Neumann index.
J. Complex Networks, 2018
2017
The Quantum Theil Index: Characterizing Graph Centralization using von Neumann Entropy.
CoRR, 2017
CoRR, 2017
Proceedings of the 2017 IEEE International Symposium on Information Theory, 2017
Proceedings of the 2017 IEEE Globecom Workshops, Singapore, December 4-8, 2017, 2017
2014
Proceedings of the 9th Conference on the Theory of Quantum Computation, 2014
2013
Experiments and analysis to characterize logic state retention limitations in 28nm process node.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2011
Quantum Discord in Quantum Information Theory - From Strong Subadditivity to the Mother Protocol.
Proceedings of the Theory of Quantum Computation, Communication, and Cryptography, 2011
A Petri Net Based Model for Multipoint Multistream Synchronization in Multimedia Conferencing.
Proceedings of the Security-Enriched Urban Computing and Smart Grid, 2011
2010
Framework for Domain Analysis of Teleteaching System: A Semiformal Approach.
Proceedings of the 2010 International Conference on Software Engineering Research & Practice, 2010
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the Contemporary Computing - Third International Conference, 2010
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
2007
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Computers, 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.
Proceedings of the 2005 Design, 2005
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005