Anil Kumar Gundu

Orcid: 0000-0002-0519-8701

According to our database1, Anil Kumar Gundu authored at least 13 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
E-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual-Function Harvesting from Breathing, and No High-Voltage CMOS Process.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022
Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater.
Integr., 2021

Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

2019
Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output Repeaters.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Energy Efficient Clock Distribution with Low-Leakage Multi-Vt Buffers.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

2016
A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variations.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A high speed low voltage latch type sense amplifier for non-volatile memory.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A regression based methodology to estimate SNM for improving yield of 6T SRAM.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2015
Statistical analysis and parametric yield estimation of standard 6T SRAM cell for different capacities.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015


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