Angshuman Parashar

According to our database, Angshuman Parashar authored at least 30 papers between 2004 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms.

Qijing Huang, Po-An Tsai, Joel S. Emer, Angshuman Parashar

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023

HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity.

Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators.

Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2022

Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators.

Prasanth Chatarasi, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Tushar Krishna, Vivek Sarkar

ACM Trans. Archit. Code Optim., 2022

A Formalism of DNN Accelerator Flexibility.

Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna

Proc. ACM Meas. Anal. Comput. Syst., 2022

Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity.

Eric Qin, Raveesh Garg, Abhimanyu Bambhaniya, Michael Pellauer, Angshuman Parashar, Sivasankaran Rajamanickam, Cong Hao, Tushar Krishna

CoRR, 2022

Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling.

Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization.

Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel S. Emer, Siddharth Joshi

Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Demystifying Map Space Exploration for NPUs.

Sheng-Chun Kao, Angshuman Parashar, Po-An Tsai, Tushar Krishna

Proceedings of the IEEE International Symposium on Workload Characterization, 2022

DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators.

Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Flexion: A Quantitative Metric for Flexibility in DNN Accelerators.

Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna

IEEE Comput. Archit. Lett., 2021

Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators.

Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Mind mappings: enabling efficient algorithm-accelerator mapping space search.

Kartik Hegde, Po-An Tsai, Sitao Huang, Vikas Chandra, Angshuman Parashar, Christopher W. Fletcher

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators.

Geonhwa Jeong, Gokcen Kestor, Prasanth Chatarasi, Angshuman Parashar, Po-An Tsai, Sivasankaran Rajamanickam, Roberto Gioiosa, Tushar Krishna

Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020

Data Orchestration in Deep Learning Accelerators

Tushar Krishna, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Ananda Samajdar

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01767-4, 2020

MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings.

Hyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, Tushar Krishna, Michael Pellauer, Angshuman Parashar

IEEE Micro, 2020

2019

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach.

Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Timeloop: A Systematic Approach to DNN Accelerator Evaluation.

Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

2017

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks.

Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2015

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures.

Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer

ACM Trans. Comput. Syst., 2015

2014

Efficient Spatial Processing Element Control via Triggered Instructions.

Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer

IEEE Micro, 2014

2013

Triggered instructions: a control paradigm for spatially-programmed architectures.

Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A Hierarchical Architectural Framework for Reconfigurable Logic Computing.

Peng Li, Angshuman Parashar, Michael Pellauer, Tao Wang, Joel S. Emer

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012

Leveraging latency-insensitivity to ease multiple FPGA design.

Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing.

Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Leap scratchpads: automatic memory and cache management for reconfigurable logic.

Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2007

Mechanisms for bounding vulnerabilities of processor structures.

Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006

SlicK: slice-based locality exploitation for efficient redundant multithreading.

Angshuman Parashar, Anand Sivasubramaniam, Sudhanva Gurumurthi

Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2004

An uncalibrated lightfield acquisition system.

Puneet Sharma, Angshuman Parashar, Subhashis Banerjee, Prem Kumar Kalra

Image Vis. Comput., 2004

A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy.

Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004