Angie Wang

Orcid: 0000-0001-5767-301X

According to our database1, Angie Wang authored at least 11 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance.
IEEE J. Solid State Circuits, 2019

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

ACED: a hardware library for generating DSP systems.
Proceedings of the 55th Annual Design Automation Conference, 2018


2017
A 65-nm CMOS Wideband TDD Front-End With Integrated T/R Switching via PA Re-Use.
IEEE J. Solid State Circuits, 2017

Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A 0.37mm<sup>2</sup> LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2<sup>n</sup>3<sup>m</sup>5<sup>k</sup> FFT accelerator integrated with a RISC-V core in 16nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A generator of memory-based, runtime-reconfigurable 2N3M5K FFT engines.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

2014
A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014


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