Angelo Geraci

Orcid: 0000-0002-6084-3953

According to our database1, Angelo Geraci authored at least 16 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
From Multiphase to Novel Single-Phase Multichannel Shift-Clock Fast Counter Time-to-Digital Converter.
IEEE Trans. Ind. Electron., August, 2024

Hybrid Spatial and Temporal Computing Histogrammer in Soft Processor Core of a FPGA Device.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024

High Spatial Resolution Detector System Based on Reconfigurable Dual-FPGA Approach for Coincidence Measurements.
Sensors, August, 2024

2023
A Study of the Latest Updates of the DAQ Firmware for the DSSC Camera at the European XFEL.
IEEE Access, 2023

2022
High-Resolution Imager Based on Time-to-Space Conversion.
IEEE Trans. Instrum. Meas., 2022

Multi-COBS: A Novel Algorithm for Byte Stuffing at High Throughput.
IEEE Access, 2022

Assessment of the Bundle SNSPD Plus FPGA-Based TDC for High-Performance Time Measurements.
IEEE Access, 2022

High-Performance Computing of Real-Time and Multichannel Histograms: A Full FPGA Approach.
IEEE Access, 2022

2021
Cross-Talk Issues in Time Measurements.
IEEE Access, 2021

Time-to-Digital Converter IP-Core for FPGA at State of the Art.
IEEE Access, 2021

Digital Instrument for Time Measurements: Small, Portable, High-Performance, Fully Programmable.
IEEE Access, 2021

2011
A New BMS Architecture Based on Cell Redundancy.
IEEE Trans. Ind. Electron., 2011

2009
High-efficiency FPGA Fully-Based Implementation of the Conjugate Gradient Method.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008
High Performance Double Precision Reduction Circuit Implementation in FPGA.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2000
Fixed-point DSP timing of pulses based on a high-precision division technique.
Proceedings of the 10th European Signal Processing Conference, 2000


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