Anelise Kologeski
According to our database1,
Anelise Kologeski
authored at least 13 papers
between 2009 and 2016.
Collaborative distances:
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Bibliography
2016
Proceedings of the 17th Latin-American Test Symposium, 2016
2015
Latency Improvement with Traffic Flow Analysis in a 3D NoC under Multiple Faulty TSVs Scenario.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
2014
Performance exploration of partially connected 3D NoCs under manufacturing variability.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
2013
Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
2012
Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnections.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
AdNoC case-study for Mpeg4 benchmark: improving performance and saving energy with an adaptive NoC.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the Links.
Proceedings of the 16th European Test Symposium, 2011
2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
2009
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009