Aneesh Raveendran

According to our database, Aneesh Raveendran authored at least 11 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications.

Venkata Reddy Kolagatla, Aneesh Raveendran, Vivian Desalphine

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing.

Venkata Reddy Kolagatla, Aneesh Raveendran, Vivian Desalphine

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

2023

Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.

Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2021

PositGen-A Verification Suite for Posit Arithmetic.

Annarao Kulkarni, Shashikala Gunderao Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor.

Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2020

A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture.

Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, David Selvakumar

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA.

Vivian Desalphine, Somya Dashora, Laxita Mali, Suhas K, Aneesh Raveendran, David Selvakumar

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU.

Aneesh Raveendran, Vinay Kumar, Vivian Desalphine, David Selvakumar

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor.

Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, A. David Selvakumar

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2015

RISC-V out-of-order data conversion co-processor.

Aneesh Raveendran, Vinayak Patil, Vivian Desalphine, P. M. Sobha, A. David Selvakumar

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Out of order floating point coprocessor for RISC V ISA.

Vinayak Patil, Aneesh Raveendran, P. M. Sobha, A. David Selvakumar, Vivian Desalphine

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015