Aneesh Aggarwal

According to our database1, Aneesh Aggarwal authored at least 35 papers between 2001 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2010
Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration.
Int. J. Parallel Program., 2010

2009
Complexity Effective Bypass Networks.
Trans. High Perform. Embed. Archit. Compil., 2009

Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Exploring the Limits of Port Reduction in Centralized Register Files.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Architectural support for low overhead detection of memory violations.
Proceedings of the Design, Automation and Test in Europe, 2009

Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration.
Proceedings of the 6th Conference on Computing Frontiers, 2009

2008
Cache Noise Prediction.
IEEE Trans. Computers, 2008

Optimizing XML processing for grid applications using an emulation framework.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Speculative instruction validation for performance-reliability trade-off.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware.
Proceedings of the High Performance Computing, 2008

2007
Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop.
SIGARCH Comput. Archit. News, 2007

Efficient XML-Based Grid Middleware Design for Multi-Core Processors.
Proceedings of the 2007 IEEE International Conference on Web Services (ICWS 2007), 2007

Increasing cache capacity through word filtering.
Proceedings of the 21th Annual International Conference on Supercomputing, 2007

McGrid: framework for optimizing grid middleware on multi-core processors.
Proceedings of the 2007 workshop on Service-oriented computing performance: aspects, 2007

2006
Address-Value Decoupling for Early Register Deallocation.
Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

Increasing the cache efficiency by eliminating noise.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors.
Proceedings of the High Performance Computing, 2006

Self-checking instructions: reducing instruction redundancy for concurrent error detection.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005
Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors.
IEEE Trans. Parallel Distributed Syst., 2005

Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency.
IEEE Trans. Computers, 2005

Reducing latencies of pipelined cache accesses through set prediction.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Restrictive Compression Techniques to Increase Level 1 Cache Capacity.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
The Efficacy of Software Prefetching and Locality Optimizations on Future Memory Systems.
J. Instr. Level Parallelism, 2004

Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors.
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Defining Wakeup Width for Efficient Dynamic Scheduling.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Single FU Bypass Networks for High Clock Rate Superscalar Processors.
Proceedings of the High Performance Computing, 2004

2003
Energy Efficient Asymmetrically Ported Register Files.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
Software caching vs. prefetching.
Proceedings of The Workshop on Memory Systems Performance (MSP 2002), 2002

Hierarchical Interconnects for On-Chip Clustering.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001
Related Field Analysis.
Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2001

An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors.
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001

Evaluating the impact of memory system performance on software prefetching and locality optimizations.
Proceedings of the 15th international conference on Supercomputing, 2001

Putting Data Value Predictors to Work in Fine-Grain Parallel Processors.
Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001


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