Aneesh Aggarwal
According to our database1,
Aneesh Aggarwal
authored at least 35 papers
between 2001 and 2017.
Collaborative distances:
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Bibliography
2017
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017
2010
Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration.
Int. J. Parallel Program., 2010
2009
Trans. High Perform. Embed. Archit. Compil., 2009
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration.
Proceedings of the 6th Conference on Computing Frontiers, 2009
2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008
Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware.
Proceedings of the High Performance Computing, 2008
2007
Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop.
SIGARCH Comput. Archit. News, 2007
Proceedings of the 2007 IEEE International Conference on Web Services (ICWS 2007), 2007
Proceedings of the 21th Annual International Conference on Supercomputing, 2007
Proceedings of the 2007 workshop on Service-oriented computing performance: aspects, 2007
2006
Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006
Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors.
Proceedings of the High Performance Computing, 2006
Self-checking instructions: reducing instruction redundancy for concurrent error detection.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006
2005
IEEE Trans. Parallel Distributed Syst., 2005
IEEE Trans. Computers, 2005
Proceedings of the 19th Annual International Conference on Supercomputing, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
2004
The Efficacy of Software Prefetching and Locality Optimizations on Future Memory Systems.
J. Instr. Level Parallelism, 2004
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the High Performance Computing, 2004
2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
2002
Proceedings of The Workshop on Memory Systems Performance (MSP 2002), 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
2001
Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2001
An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors.
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001
Evaluating the impact of memory system performance on software prefetching and locality optimizations.
Proceedings of the 15th international conference on Supercomputing, 2001
Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001