Andy Gean Ye
Orcid: 0000-0002-2959-5736
According to our database1,
Andy Gean Ye
authored at least 33 papers
between 1999 and 2024.
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Bibliography
2024
Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm.
ACM Trans. Reconfigurable Technol. Syst., March, 2024
2022
Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs.
Microprocess. Microsystems, July, 2022
Integr., 2022
Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022
2021
Integr., 2021
2020
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
2019
Proceedings of the Image Analysis and Recognition - 16th International Conference, 2019
2018
An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures.
ACM Trans. Reconfigurable Technol. Syst., 2018
2017
A study on the accuracy of minimum width transistor area in estimating FPGA layout area.
Microprocess. Microsystems, 2017
Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
2016
Circuits Syst. Signal Process., 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
A new adaptive Decision Feedback Equalizer using hexagon eye-opening monitor for multi Gbps data links.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2012
Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs.
Microprocess. Microsystems, 2012
Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications.
Microprocess. Microsystems, 2012
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding.
Integr., 2012
Effect of scaling on the area and performance of the H.264/AVC full-search fractional motion estimation algorithm on field-programmable gate arrays.
IET Comput. Digit. Tech., 2012
2011
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling.
ACM Trans. Reconfigurable Technol. Syst., 2011
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
2010
Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2010
The effect of multi-bit based connections on the area efficiency of FPGAs utilizing unidirectional routing resources.
Proceedings of the International Conference on Field-Programmable Technology, 2010
Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010
2009
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
2006
Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2006
2005
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002
1999
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999