Andrzej Pulka

According to our database, Andrzej Pulka authored at least 19 papers between 1999 and 2023.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2023

Validation of Task Scheduling Techniques in Multithread Time Predictable Systems.

Ernest Antolak, Andrzej Pulka

IEEE Access, 2023

2021

Energy-Efficient Task Scheduling in Design of Multithread Time Predictable Real-Time Systems.

Ernest Antolak, Andrzej Pulka

IEEE Access, 2021

2020

Digitally programmable modified current differencing transconductance amplifier in 40-nm technology: design flow, parameter analyses and applications.

Andrzej Malcher, Adam Kristof, Andrzej Pulka

IET Circuits Devices Syst., 2020

Flexible hardware approach to multi-core time-predictable systems design based on the interleaved pipeline processing.

Ernest Antolak, Andrzej Pulka

IET Circuits Devices Syst., 2020

2016

Preface.

Andrzej Pulka

Microprocess. Microsystems, 2016

2014

Selection of search strategies for solving 3-SAT problems.

Andrzej Pulka

Int. J. Appl. Math. Comput. Sci., 2014

2013

Analysis of timing resources for highly predictable real-time systems models.

Lukasz Golly, Andrzej Pulka

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2012

Dynamic rescheduling of tasks in time predictable embedded systems.

Andrzej Pulka, Adam Milik

Proceedings of the 11th IFAC Conference on Programmable Devices and Embedded Systems, 2012

2011

Automatic implementation of arithmetic operation in reconfigurable logic controllers.

Adam Milik, Andrzej Pulka

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

On efficient implementation of search algorithm for genome patterns.

Adam Milik, Andrzej Pulka

Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

2009

The reconfigurable hardware accelerator for searching genome patterns.

Adam Milik, Andrzej Pulka

Proceedings of the 9th IFAC Workshop on Programmable Devices and Embedded Systems, 2009

Multithread RISC architecture based on programmable interleaved pipelining.

Andrzej Pulka, Adam Milik

Proceedings of the 16th IEEE International Conference on Electronics, 2009

A heterogenous approach to symbolic calculations based on structural numbers.

Andrzej Pulka, Lukasz Golly

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams.

Andrzej Pulka, Adam Milik

Proceedings of the Forum on specification and Design Languages, 2008

2007

A Heuristic Fault Dictionary Reduction Methodology.

Andrzej Pulka

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Common HDL-Matlab Simulation Environment.

Adam Milik, Andrzej Pulka

Proceedings of the Forum on specification and Design Languages, 2007

A common-sense based approach to the automated test-point selection in fault diagnosis.

Andrzej Pulka, Jerzy Rutkowski

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

SystemC models generation based on libraries of templates.

Andrzej Pulka

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

1999

Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique.

Jerzy J. Dabrowski, Andrzej Pulka

Proceedings of the 1999 Design, 1999