Andrzej Hlawiczka

According to our database, Andrzej Hlawiczka authored at least 23 papers between 1978 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Reduced-size signature-based diagnostic dictionary for interconnection testing.

Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

How to reduce size of a signature-based diagnostic dictionary used for testing of connections.

Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

Effective BIST for crosstalk faults in interconnects.

Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

Interconnect Faults Identification and Localization Using Modified Ring LFSRs.

Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

Test Pattern Generator for Delay Faults.

Tomasz Rudnicki, Andrzej Hlawiczka

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Avoiding Crosstalk Influence on Interconnect Delay Fault Testing.

Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Test-per-Clock Detection, Localization and Identification of Interconnect Faults.

Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 11th European Test Symposium, 2006

Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor.

Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2004

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.

Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa

J. Electron. Test., 2004

2002

Efficient test pattern generators based on specific cellular automata structures.

Tomasz Garbolino, Andrzej Hlawiczka

Microelectron. Reliab., 2002

Dependable testing of compactor MISR: an imperceptible problem?

Andrzej Hlawiczka, Michal Kopec

Proceedings of the 7th European Test Workshop, 2002

2000

Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path.

Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof

Proceedings of the 5th European Test Workshop, 2000

Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata.

Andrzej Hlawiczka, Michal Kopec

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits.

Tomasz Garbolino, Andrzej Hlawiczka

Proceedings of the Dependable Computing, 1999

1997

A linear code-preserving signature analyzer COPMISR.

Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Low Cost Bist for Edac Circuits.

Dariusz Badura, Andrzej Hlawiczka

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1994

Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures.

Andrzej Hlawiczka, Jacek Binda

Proceedings of the Field-Programmable Logic, 1994

1992

Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks.

Andrzej Hlawiczka

IEEE Trans. Computers, 1992

1989

Signature Analysis Testing with Bottom-Top Exclusive Or Type MISR.

Andrzej Hlawiczka

Proceedings of the Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, 1989

1987

Universal Test Controller Chip for Board Self Test.

Andrzej Hlawiczka, Dariusz Badura

Proceedings of the Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, 1987

1986

Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer.

Andrzej Hlawiczka

IEEE Trans. Computers, 1986

1984

Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer.

Andrzej Hlawiczka

Proceedings of the Fehlertolerierende Rechensysteme, 1984

1978

Comments on "Procedures for Eliminating Static and Dynamic-Hazards in Test Generation".

Andrzej Hlawiczka

IEEE Trans. Computers, 1978