Andrew Suchanek

Orcid: 0000-0002-9397-2604

According to our database1, Andrew Suchanek authored at least 3 papers between 2017 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

2017
2018
2019
2020
2021
2022
2023
2024
2025
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1
2
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
Fail-Safe Logic Design Strategies Within Modern FPGA Architectures.
IEEE Access, 2025

2023
A 0.2-2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55-448.6 ns Programmable Delay Range and 330 ns/mm<sup>2</sup> Area Efficiency.
IEEE J. Solid State Circuits, 2023

2017
Recent Advances in Low Power Asynchronous Circuit Design.
J. Low Power Electron., 2017


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