Andrew Reynolds

Orcid: 0000-0002-3529-8682

Affiliations:
  • University of Iowa, Department of Computer Science, Iowa City, USA


According to our database1, Andrew Reynolds authored at least 88 papers between 2011 and 2024.

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Bibliography

2024
IsaRare: Automatic Verification of SMT Rewrites in Isabelle/HOL.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2024

Verifying SQL queries using theories of tables and relations.
Proceedings of the LPAR 2024: Proceedings of 25th Conference on Logic for Programming, 2024

Satisfiability Modulo Theories: A Beginner's Tutorial.
Proceedings of the Formal Methods - 26th International Symposium, 2024

The SemGuS Toolkit.
Proceedings of the Computer Aided Verification - 36th International Conference, 2024

2023
Combining Stable Infiniteness and (Strong) Politeness.
J. Autom. Reason., December, 2023

Generating and Exploiting Automated Reasoning Proof Certificates.
Commun. ACM, October, 2023

Reasoning About Vectors: Satisfiability Modulo a Theory of Sequences.
J. Autom. Reason., September, 2023

Synthesising Programs with Non-trivial Constants.
J. Autom. Reason., June, 2023

The SyGuS Language Standard Version 2.1.
CoRR, 2023

Automatic Verification of SMT Rewrites in Isabelle/HOL.
Proceedings of the 21st International Workshop on Satisfiability Modulo Theories (SMT 2023) co-located with the 29th International Conference on Automated Deduction (CADE 2023), 2023

Selecting Quantifiers for Instantiation in SMT.
Proceedings of the 21st International Workshop on Satisfiability Modulo Theories (SMT 2023) co-located with the 29th International Conference on Automated Deduction (CADE 2023), 2023

An Interactive SMT Tactic in Coq using Abductive Reasoning.
Proceedings of the LPAR 2023: Proceedings of 24th International Conference on Logic for Programming, 2023

Partitioning Strategies for Distributed SMT Solving.
Proceedings of the Formal Methods in Computer-Aided Design, 2023

A Procedure for SyGuS Solution Fitting via Matching and Rewrite Rule Discovery.
Proceedings of the Formal Methods in Computer-Aided Design, 2023

2022
Bit-Precise Reasoning via Int-Blasting.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2022

Satisfiability and Synthesis Modulo Oracles.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2022

cvc5: A Versatile and Industrial-Strength SMT Solver.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2022

Reconstructing Fine-Grained Proofs of Rewrites Using a Domain-Specific Language.
Proceedings of the 22nd Formal Methods in Computer-Aided Design, 2022

Even Faster Conflicts and Lazier Reductions for String Solvers.
Proceedings of the Computer Aided Verification - 34th International Conference, 2022

Reasoning About Vectors Using an SMT Theory of Sequences.
Proceedings of the Automated Reasoning - 11th International Joint Conference, 2022

Cooperating Techniques for Solving Nonlinear Real Arithmetic in the cvc5 SMT Solver (System Description).
Proceedings of the Automated Reasoning - 11th International Joint Conference, 2022

Flexible Proof Production in an Industrial-Strength SMT Solver.
Proceedings of the Automated Reasoning - 11th International Joint Conference, 2022

2021
Syntax-Guided Quantifier Instantiation (TACAS 2021 Artifact).
Dataset, February, 2021

Towards Satisfiability Modulo Parametric Bit-vectors.
J. Autom. Reason., 2021

On solving quantified bit-vector constraints using invertibility conditions.
Formal Methods Syst. Des., 2021

lazybvtoint at the SMT Competition 2020.
CoRR, 2021

Syntax-Guided Quantifier Instantiation.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2021

Characteristic Subsets of SMT-LIB Benchmarks.
Proceedings of the 19th International Workshop on Satisfiability Modulo Theories co-located with 33rd International Conference on Computer Aided Verification(CAV 2021), 2021

Fair and Adventurous Enumeration of Quantifier Instantiations.
Proceedings of the Formal Methods in Computer Aided Design, 2021

Politeness and Stable Infiniteness: Stronger Together.
Proceedings of the Automated Deduction - CADE 28, 2021

2020
Reductions for Strings and Regular Expressions Revisited.
Proceedings of the 2020 Formal Methods in Computer Aided Design, 2020

SYSLITE: Syntax-Guided Synthesis of PLTL Formulas from Finite Traces.
Proceedings of the 2020 Formal Methods in Computer Aided Design, 2020

A Decision Procedure for String to Code Point Conversion.
Proceedings of the Automated Reasoning - 10th International Joint Conference, 2020

Scalable Algorithms for Abduction via Enumerative Syntax-Guided Synthesis.
Proceedings of the Automated Reasoning - 10th International Joint Conference, 2020

2019
Refutation-based synthesis in SMT.
Formal Methods Syst. Des., 2019

CVC4SY for SyGuS-COMP 2019.
CoRR, 2019


Syntax-Guided Rewrite Rule Enumeration for SMT Solvers.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2019, 2019

Extending enumerative function synthesis via SMT-driven classification.
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019

High-Level Abstractions for Simplifying Extended String Constraints in SMT.
Proceedings of the Computer Aided Verification - 31st International Conference, 2019

cvc4sy: Smart and Fast Term Enumeration for Syntax-Guided Synthesis.
Proceedings of the Computer Aided Verification - 31st International Conference, 2019

Invertibility Conditions for Floating-Point Formulas.
Proceedings of the Computer Aided Verification - 31st International Conference, 2019

Towards Bit-Width-Independent Proofs in SMT Solvers.
Proceedings of the Automated Deduction - CADE 27, 2019

Extending SMT Solvers to Higher-Order Logic.
Proceedings of the Automated Deduction - CADE 27, 2019

2018
Reasoning with Finite Sets and Cardinality Constraints in SMT.
Log. Methods Comput. Sci., 2018

CVC4 at the SMT Competition 2018.
CoRR, 2018

Revisiting Enumerative Instantiation.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2018

The FMCAD 2018 Graduate Student Forum.
Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

Solving Quantified Bit-Vectors Using Invertibility Conditions.
Proceedings of the Computer Aided Verification - 30th International Conference, 2018

Datatypes with Shared Selectors.
Proceedings of the Automated Reasoning - 9th International Joint Conference, 2018

2017
Constraint solving for finite model finding in SMT solvers.
Theory Pract. Log. Program., 2017

A Decision Procedure for (Co)datatypes in SMT Solvers.
J. Autom. Reason., 2017

Solving quantified linear arithmetic by counterexample-guided instantiation.
Formal Methods Syst. Des., 2017

SyGuS Techniques in the Core of an SMT Solver.
Proceedings of the Proceedings Sixth Workshop on Synthesis, 2017

Reasoning in the Bernays-Schönfinkel-Ramsey Fragment of Separation Logic.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2017

Congruence Closure with Free Variables.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2017

Quantifier Instantiation Beyond E-Matching.
Proceedings of the 15th International Workshop on Satisfiability Modulo Theories affiliated with the International Conference on Computer-Aided Verification (CAV 2017), Heidelberg, Germany, July 22, 2017

Designing Theory Solvers with Extensions.
Proceedings of the Frontiers of Combining Systems - 11th International Symposium, 2017

Scaling Up DPLL(T) String Solvers Using Context-Dependent Simplification.
Proceedings of the Computer Aided Verification - 29th International Conference, 2017

SMTCoq: A Plug-In for Integrating SMT Solvers into Coq.
Proceedings of the Computer Aided Verification - 29th International Conference, 2017

Challenges for Fast Synthesis Procedures in SMT.
Proceedings of the ARCADE 2017, 2017

Relational Constraint Solving in SMT.
Proceedings of the Automated Deduction - CADE 26, 2017

2016
An efficient SMT solver for string constraints.
Formal Methods Syst. Des., 2016

Reasoning in the Bernays-Schoenfinkel-Ramsey Fragment of Separation Logic.
CoRR, 2016

A Decision Procedure for Separation Logic in SMT.
CoRR, 2016

Extending SMTCoq, a Certified Checker for SMT (Extended Abstract).
Proceedings of the Proceedings First International Workshop on Hammers for Type Theories, 2016

Efficient solving of string constraints for security analysis.
Proceedings of the Symposium and Bootcamp on the Science of Security, 2016

Lazy proofs for DPLL(T)-based SMT solvers.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Model Finding for Recursive Functions in SMT.
Proceedings of the Automated Reasoning - 8th International Joint Conference, 2016

Conflicts, Models and Heuristics for Quantifier Instantiation in SMT.
Proceedings of the Vampire@IJCAR 2016. Proceedings of the 3rd Vampire Workshop, 2016

A New Decision Procedure for Finite Sets and Cardinality Constraints in SMT.
Proceedings of the Automated Reasoning - 8th International Joint Conference, 2016

A Decision Procedure for Separation Logic in SMT.
Proceedings of the Automated Technology for Verification and Analysis, 2016

2015
On Counterexample Guided Quantifier Instantiation for Synthesis in CVC4.
CoRR, 2015

An Instantiation-Based Approach for Solving Quantified Linear Arithmetic.
CoRR, 2015

Induction for SMT Solvers.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2015

Fine Grained SMT Proofs for the Theory of Fixed-Width Bit-Vectors.
Proceedings of the Logic for Programming, Artificial Intelligence, and Reasoning, 2015

A Decision Procedure for Regular Membership and Length Constraints over Unbounded Strings.
Proceedings of the Frontiers of Combining Systems - 10th International Symposium, 2015

Counterexample-Guided Quantifier Instantiation for Synthesis in SMT.
Proceedings of the Computer Aided Verification - 27th International Conference, 2015

Deciding Local Theory Extensions via E-matching.
Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014
Approaches for Synthesis Conjectures in an SMT Solver.
CoRR, 2014

Finding conflicting instances of quantified formulas in SMT.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

A tour of CVC4: How it works, and how to use it.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

A DPLL(T) Theory Solver for a Theory of Strings and Regular Expressions.
Proceedings of the Computer Aided Verification - 26th International Conference, 2014

2013
SMT proof checking using a logical framework.
Formal Methods Syst. Des., 2013

Finite Model Finding in SMT.
Proceedings of the Computer Aided Verification - 25th International Conference, 2013

Quantifier Instantiation Techniques for Finite Model Finding in SMT.
Proceedings of the Automated Deduction - CADE-24, 2013

2012
LFSC for SMT Proofs: Work in Progress.
Proceedings of the Second International Workshop on Proof Exchange for Theorem Proving, 2012

2011
Proceedings of the Computer Aided Verification - 23rd International Conference, 2011


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