Andrew Laffely

According to our database, Andrew Laffely authored at least 6 papers between 2003 and 2004.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2004

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations.

Prashant Jain, Andrew Laffely, Wayne P. Burleson, Russell Tessier, Dennis Goeckel

J. VLSI Signal Process., 2004

An architecture and compiler for scalable on-chip communication.

Jian Liang, Andrew Laffely, Sriram Srinivasan, Russell Tessier

IEEE Trans. Very Large Scale Integr. Syst., 2004

NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods.

Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson

Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

2003

Using System On-A-Chip As A Vehicle For VLSI Design Education.

Andrew Laffely, Wayne P. Burleson

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Targeting Tiled Architectures in Design Exploration.

Lilian Bossuet, Wayne P. Burleson, Guy Gogniat, Vikas Anand, Andrew Laffely, Jean Luc Philippe

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores.

Andrew Laffely, Jian Liang, Russell Tessier, Wayne P. Burleson

Proceedings of the 2003 International Conference on Image Processing, 2003