Andrew Herdrich
Affiliations:- Intel, Santa Clara, CA, USA
According to our database1,
Andrew Herdrich
authored at least 11 papers
between 2009 and 2023.
Collaborative distances:
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Bibliography
2023
Neurocomputing, November, 2023
2021
IEEE Micro, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization.
Proceedings of the 6th IEEE Conference on Network Softwarization, 2020
2017
QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications.
IEEE Syst. J., 2017
2016
Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016
2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
2012
Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012
2010
SIGMETRICS Perform. Evaluation Rev., 2010
2009
Proceedings of the 23rd international conference on Supercomputing, 2009