Andrew Ferraiuolo

According to our database, Andrew Ferraiuolo authored at least 14 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

MPruner: Optimizing Neural Network Size with CKA-Based Mutual Information Pruning.

Seungbeom Hu, ChanJun Park, Andrew Ferraiuolo, Sang-Ki Ko, Jinwoo Kim, Haein Song, Jieung Kim

CoRR, 2024

2022

Policy Transparency: Authorization Logic Meets General Transparency to Prove Software Supply Chain Integrity.

Andrew Ferraiuolo, Razieh Behjati, Tiziano Santoro, Ben Laurie

Proceedings of the 2022 ACM Workshop on Software Supply Chain Offensive Research and Ecosystem Defenses, 2022

2018

Secure Autonomous Cyber-Physical Systems Through Verifiable Information Flow Control.

Jed Liu, Joe Corbett-Davies, Andrew Ferraiuolo, Alexander Ivanov, Mulong Luo, G. Edward Suh, Andrew C. Myers, Mark E. Campbell

Proceedings of the 2018 Workshop on Cyber-Physical Systems Security and PrivaCy, 2018

HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security.

Andrew Ferraiuolo, Mark Zhao, Andrew C. Myers, G. Edward Suh

Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018

2017

Komodo: Using verification to disentangle secure-enclave hardware from software.

Andrew Ferraiuolo, Andrew Baumann, Chris Hawblitzel, Bryan Parno

Proceedings of the 26th Symposium on Operating Systems Principles, 2017

Secure Information Flow Verification with Mutable Dependent Types.

Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh

Proceedings of the 54th Annual Design Automation Conference, 2017

Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis.

Andrew Ferraiuolo, Rui Xu, Danfeng Zhang, Andrew C. Myers, G. Edward Suh

Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016

Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller.

Andrew Ferraiuolo, Yao Wang, Danfeng Zhang, Andrew C. Myers, G. Edward Suh

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

SecDCP: secure dynamic cache partitioning for efficient timing channel protection.

Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, G. Edward Suh

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Detecting Hardware Trojans using On-chip Sensors in an ASIC Design.

Shane Kelly, Xuehui Zhang, Mohammad Tehranipoor, Andrew Ferraiuolo

J. Electron. Test., 2015

2014

Timing channel protection for a shared memory controller.

Yao Wang, Andrew Ferraiuolo, G. Edward Suh

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Low-overhead and high coverage run-time race detection through selective meta-data management.

Ruirui C. Huang, Erik Halberg, Andrew Ferraiuolo, G. Edward Suh

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Detection of trojans using a combined ring oscillator network and off-chip transient power analysis.

Xuehui Zhang, Andrew Ferraiuolo, Mohammad Tehranipoor

ACM J. Emerg. Technol. Comput. Syst., 2013

2012

Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC.

Andrew Ferraiuolo, Xuehui Zhang, Mohammad Tehranipoor

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012