Andrew D. Hilton

According to our database, Andrew D. Hilton authored at least 16 papers between 2007 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Gemini: A Functional Programming Language for Hardware Description.

Aditya Srinivasan, Andrew D. Hilton

CoRR, 2019

DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management.

Ziqiang Huang, José A. Joao, Alejandro Rico, Andrew D. Hilton, Benjamin C. Lee

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Translation from Problem to Code in Seven Steps.

Andrew D. Hilton, Genevieve M. Lipp, Susan H. Rodger

Proceedings of the ACM Conference on Global Computing Education, 2019

2018

A technique for translation from problem to code.

Andrew D. Hilton, Genevieve M. Lipp, Susan H. Rodger

Proceedings of the 23rd Annual ACM Conference on Innovation and Technology in Computer Science Education, 2018

MAPS: Understanding Metadata Access Patterns in Secure Memory.

Tamara Silbergleit Lehman, Andrew D. Hilton, Benjamin C. Lee

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

2016

TREES: A CPU/GPU Task-Parallel Runtime with Explicit Epoch Synchronization.

Blake A. Hechtman, Andrew D. Hilton, Daniel J. Sorin

CoRR, 2016

PoisonIvy: Safe speculation for secure memory.

Tamara Silbergleit Lehman, Andrew D. Hilton, Benjamin C. Lee

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Decoupling Loads for Nano-Instruction Set Computers.

Ziqiang Huang, Andrew D. Hilton, Benjamin C. Lee

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015

Multi-program benchmark definition.

Adam N. Jacobvitz, Andrew D. Hilton, Daniel J. Sorin

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

2012

Flexible register management using reference counting.

Steven J. Battle, Andrew D. Hilton, Mark Hempstead, Amir Roth

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2010

iCFP: Tolerating All-Level Cache Misses in In-Order Processors.

Andrew D. Hilton, Santosh Nagarakatte, Amir Roth

IEEE Micro, 2010

SMT-Directory: Efficient Load-Load Ordering for SMT.

Andrew D. Hilton, Amir Roth

IEEE Comput. Archit. Lett., 2010

BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution.

Andrew D. Hilton, Amir Roth

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009

Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors.

Andrew D. Hilton, Amir Roth

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

CPROB: Checkpoint Processing with Opportunistic Minimal Recovery.

Andrew D. Hilton, Neeraj Eswaran, Amir Roth

Proceedings of the PACT 2009, 2009

2007

Ginger: control independence using tag rewriting.

Andrew D. Hilton, Amir Roth

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007