Andrew Beaumont-Smith

According to our database1, Andrew Beaumont-Smith authored at least 7 papers between 1995 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2005
Pain versus Gain in the Hardware Design of FPUs and Supercomputers.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2001
A VLSI chip implementation of an A/D converter error table compensator.
Comput. Stand. Interfaces, 2001

Parallel Prefix Adder Design.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

1999
An array processor architecture for support vector learning.
Proceedings of the Third International Conference on Knowledge-Based Intelligent Information Engineering Systems, 1999

Reduced Latency IEEE Floating-Point Standard Adder Architectures.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1997
A GaAs 32-bit Adder.
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1995
Biologically inspired obstacle avoidance - a technology independent paradigm.
Proceedings of the Mobile Robots X, Philadephia, PA, USA, October 23, 1995, Proceedings, 1995


  Loading...