Andres Goens

Orcid: 0000-0002-0409-1363

Affiliations:
  • Dresden University of Technology, Germany (PhD 2021)


According to our database1, Andres Goens authored at least 34 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
Guided Equality Saturation.
Proc. ACM Program. Lang., January, 2024

Bridging Syntax and Semantics of Lean Expressions in E-Graphs.
CoRR, 2024

2023
Compound Memory Models.
Proc. ACM Program. Lang., 2023

2022
mpsym: Improving Design-Space Exploration of Clustered Manycores With Arbitrary Topologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Improving Model-Based Software Synthesis: A Focus on Mathematical Structures.
PhD thesis, 2021

Domain-specific Hybrid Mapping for Energy-efficient Baseband Processing in Wireless Networks.
ACM Trans. Embed. Comput. Syst., 2021

A Reinforcement Learning Environment for Polyhedral Optimizations.
CoRR, 2021

Embeddings of Task Mappings to Multicore Systems.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Mocasin - Rapid Prototyping of Rapid Prototyping Tools: A Framework for Exploring New Approaches in Mapping Software to Heterogeneous Multi-cores.
Proceedings of the DroneSE and RAPIDO '21: Methods and Tools, 2021

PolyGym: Polyhedral Optimizations as an Environment for Reinforcement Learning.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020
Modem Design in the Era of 5G and Beyond: The Need for a Formal Approach.
Proceedings of the 27th International Conference on Telecommunications, 2020

ComPy-Learn: A toolbox for exploring machine learning representations for compilers.
Proceedings of the Forum for Specification and Design Languages, 2020

Achieving Determinism in Adaptive AUTOSAR.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Generalized Data Placement Strategies for Racetrack Memories.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Compiler-based graph representations for deep learning models of code.
Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020

2019
Category-Theoretic Foundations of "STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism".
CoRR, 2019

On Compact Mappings for Multicore Systems.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

A case study on machine learning for synthesizing benchmarks.
Proceedings of the 3rd ACM SIGPLAN International Workshop on Machine Learning and Programming Languages, 2019

STCLang: state thread composition as a foundation for monadic dataflow parallelism.
Proceedings of the 12th ACM SIGPLAN International Symposium on Haskell, 2019

Actors Revisited for Time-Critical Systems.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Reactors: A Deterministic Model for Composable Reactive Systems.
Proceedings of the Cyber Physical Systems. Model-Based Design - 9th International Workshop, 2019

2018
A Hardware/Software Stack for Heterogeneous Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

On the Representation of Mappings to Multicores.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

Compiling for concise code and efficient I/O.
Proceedings of the 27th International Conference on Compiler Construction, 2018

2017
Symmetry in Software Synthesis.
ACM Trans. Archit. Code Optim., 2017

Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

2016
An optimal allocation of memory buffers for complex multicore platforms.
J. Syst. Archit., 2016

High-level NoC model for MPSoC compilers.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Why Comparing System-Level MPSoC Mapping Approaches is Difficult: A Case Study.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

2015
Buffer Allocation Based On-Chip Memory Optimization for Many-Core Platforms.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

2014
Optimized buffer allocation in multicore platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


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