Andres F. Gomez

According to our database1, Andres F. Gomez authored at least 14 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects.
J. Electron. Test., 2019

2018
Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects.
ACM Trans. Design Autom. Electr. Syst., 2018

Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

A metric-guided gate-sizing methodology for aging guardband reduction.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2016
Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations.
Microelectron. Reliab., 2016

Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage.
J. Low Power Electron., 2016

A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage.
Proceedings of the 17th Latin-American Test Symposium, 2016

Critical path selection under NBTI/PBTI aging for adaptive frequency tuning.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Circuit performance optimization for local intra-die process variations using a gate selection metric.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability.
Proceedings of the 16th Latin-American Test Symposium, 2015


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