Andrej Zemva

Affiliations:
  • Faculty of Electrical Enginering, University of Ljubljana, Ljubljana, Slovenia


According to our database1, Andrej Zemva authored at least 26 papers between 1994 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Image Acquisition Device for Smart-City Access Control Applications Based on Iris Recognition.
Sensors, 2021

2020
Message from the Program Chairs.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
Online VHDL Generator and Analysis Tool.
Proceedings of the 8th Mediterranean Conference on Embedded Computing, 2019

2017
Pipeline circuit synthesis from Python code.
Proceedings of the 6th Mediterranean Conference on Embedded Computing, 2017

2015
Configurable hardware components generator in Python.
Proceedings of the 4th Mediterranean Conference on Embedded Computing, 2015

2012
A systematic approach to configurable functional verification of HW IP blocks at transaction level.
Comput. Electr. Eng., 2012

Verification structures for design of video processing circuits.
Proceedings of the 2012 Proceedings of the 35th International Convention, 2012

Communication-control concept in distribution network with dispersed energy resources.
Proceedings of the 3rd IEEE PES Innovative Smart Grid Technologies Europe, 2012

2011
Simulation and Verification of a Dynamic Model of the Electric Forklift Truck.
Intell. Autom. Soft Comput., 2011

2010
Elliptic IIR filter sharpening implemented on FPGA.
Digit. Signal Process., 2010

FPGA-oriented HW/SW implementation of ECG beat detection and classification algorithm.
Digit. Signal Process., 2010

2009
The integration of home-automation and IPTV system and services.
Comput. Stand. Interfaces, 2009

2008
Functional Verification of a USB Host Controller.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
FPGA-oriented HW/SW implementation of the MPEG-4 video decoder.
Microprocess. Microsystems, 2007

Hardware Implementation of a Modified Delay-Coordinate Mapping-Based QRS Complex Detection Algorithm.
EURASIP J. Adv. Signal Process., 2007

2005
Test generation for technology-specific multi-faults based on detectable perturbations.
Microelectron. Reliab., 2005

Profiling soft-core processor applications for hardware/software partitioning.
J. Syst. Archit., 2005

A systematic approach to profiling for hardware/software partitioning.
Comput. Electr. Eng., 2005

2003
HW/SW Codesign of the MPEG-2 Video Decoder.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder.
Proceedings of the 2003 Design, 2003

2000
Educational Programmable Hardware Prototyping and Verification System.
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
HW/SW Co-Simulation of Target C++ Applications and Synthesizable HDL with Performance Estimation.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
Programmabel Prototyping System for Image Processing.
Proceedings of the Field-Programmable Logic and Applications, 1998

1996
An Experimental Programmable Environment for Prototyping Digital Circuits.
Proceedings of the Field-Programmable Logic, 1996

1995
Detectable perturbations: a paradigm for technology-specific multi-fault test generation.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1994
A Functionality Fault Model: Feasibility and Applications.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994


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