Andrei Sergeevich Terechko

Orcid: 0000-0001-5233-8976

According to our database1, Andrei Sergeevich Terechko authored at least 23 papers between 2001 and 2024.

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Bibliography

2024
The Safety Shell: An Architecture to Handle Functional Insufficiencies in Automated Driving.
IEEE Trans. Intell. Transp. Syst., July, 2024

Characterization and Mitigation of Insufficiencies in Automated Driving Systems.
CoRR, 2024

Evaluation of the Safety Shell Architecture for Automated Driving in a Realistic Simulator.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2024

2023
The Safety Shell: an Architecture to Handle Functional Insufficiencies in Automated Driving.
CoRR, 2023

2022
Detection and Mitigation of Functional Insufficiencies in Autonomous Vehicles: The Safety Shell.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2022

2020
A Formally Verified Fail-Operational Safety Concept for Automated Driving.
CoRR, 2020

A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A Retargetable Fault Injection Framework for Safety Validation of Autonomous Vehicles.
Proceedings of the IEEE International Conference on Software Architecture Companion, 2019


2014
Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project.
Microprocess. Microsystems, 2014

Energy-aware parallelization flow and toolset for C code.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

2013
EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures.
ACM Trans. Embed. Comput. Syst., 2012

2011
A Multithreaded Multicore System for Embedded Media Processing.
Trans. High Perform. Embed. Archit. Compil., 2011

A Highly Scalable Parallel Implementation of H.264.
Trans. High Perform. Embed. Archit. Compil., 2011

2009
Parallel H.264 Decoding on an Embedded Multicore Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

A Hardware Task Scheduler for Embedded Video Processing.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2008
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Inter-cluster communication in VLIW architectures.
ACM Trans. Archit. Code Optim., 2007

2005
Evaluation of Speed and Area of Clustered VLIW Processors.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2003
Inter-Cluster Communication Models for Clustered VLIW Processors.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Cluster assignment of global values for clustered VLIW processors.
Proceedings of the International Conference on Compilers, 2003

2001
PRMDL: a machine description language for clustered VLIW architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001


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