Andrei Radulescu
According to our database1,
Andrei Radulescu
authored at least 32 papers
between 1998 and 2021.
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Bibliography
2021
Developing and Applying Custom Static Analysis Tools for Industrial Multi-Language Code Bases.
Proceedings of the 20th Belgium-Netherlands Software Evolution Workshop, 2021
2018
Model-based software restructuring: Lessons from cleaning up COM interfaces in industrial legacy code.
Proceedings of the 25th International Conference on Software Analysis, 2018
2016
Proceedings of the Theory and Practice of Model Transformations, 2016
2010
Proceedings of the Formal Methods for Industrial Critical Systems, 2010
2007
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic.
VLSI Design, 2007
VLSI Design, 2007
2006
Proceedings of the International Symposium on Industrial Embedded Systems, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
ACM Trans. Design Autom. Electr. Syst., 2005
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Des. Test Comput., 2005
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification.
Proceedings of the 2005 Design, 2005
A unified approach to constrained mapping and routing on network-on-chip architectures.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Proceedings of the Correct Hardware Design and Verification Methods, 2005
2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
2003
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.
Proceedings of the 2003 Design, 2003
Proceedings of the Networks on Chip, 2003
2002
IEEE Trans. Parallel Distributed Syst., 2002
2001
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
Proceedings of the 2001 International Conference on Parallel Processing, 2001
2000
Proceedings of the 9th Heterogeneous Computing Workshop, 2000
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000
1999
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999
Proceedings of the 13th international conference on Supercomputing, 1999
Proceedings of the International Conference on Parallel Processing 1999, 1999
1998
Proceedings of the 5th International Conference On High Performance Computing, 1998