Andreas Tockhorn
According to our database1,
Andreas Tockhorn
authored at least 9 papers
between 2006 and 2013.
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Bibliography
2013
System level modeling of Networks-on-Chip for power estimation and design space exploration.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
2012
Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
Proceedings of the Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
2009
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
2008
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008
2007
Proceedings of the 2007 IEEE Workshop on Evolvable and Adaptive Hardware, 2007
2006
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006